Motorcomm YT8521SH-CA/YT8521SC-CA Datasheet
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6. Register Overview ............................................................................................................................................... 18
6.1. Common Register ..................................................................................................................................... 18
6.1.1. SMI_SDS_PHY (EXT_0xA000) ................................................................................................... 18
6.1.2. Chip_Config (EXT_0xA001) ........................................................................................................ 18
6.1.3. SDS_Config (EXT_0xA002) ......................................................................................................... 19
6.1.4. RGMII_Config1 (EXT_0xA003) .................................................................................................. 19
6.1.5. RGMII_Config2 (EXT_0xA004) .................................................................................................. 20
6.1.6. MDIO_Cfg_And_RGMII_OOB_Mon (EXT_0xA005) ................................................................ 20
6.1.7. Misc_Config (EXT_0xA006) ........................................................................................................ 21
6.1.8. MAC_Address_Cfg1 (EXT_0xA007) ........................................................................................... 21
6.1.9. MAC_Address_Cfg2 (EXT_0xA008) ........................................................................................... 21
6.1.10. MAC_Address_Cfg3 (EXT_0xA009) ......................................................................................... 22
6.1.11. WOL_Cfg (EXT_0xA00A) ......................................................................................................... 22
6.1.12. LED_GENERAL_CFG (EXT_0xA00B) .................................................................................... 22
6.1.13. LED0_CFG (EXT_0xA00C) ....................................................................................................... 23
6.1.14. LED1_CFG (EXT_0xA00D) ....................................................................................................... 24
6.1.15. LED2_CFG (EXT_0xA00E) ....................................................................................................... 24
6.1.16. LED_BLINK_CFG (EXT_0xA00F) ........................................................................................... 25
6.1.17. Pad Drive Strength Cfg (EXT_0xA010) ...................................................................................... 25
6.1.18. SyncE_CFG (EXT_0xA012) ....................................................................................................... 26
6.2. UTP MII Register ..................................................................................................................................... 26
6.2.1. Basic Control Register (0x00) ....................................................................................................... 26
6.2.2. Basic Status Register (0x01) .......................................................................................................... 27
6.2.3. PHY Identification Register1 (0x02) ............................................................................................. 28
6.2.4. PHY Identification Register2 (0x03) ............................................................................................. 28
6.2.5. Auto-Negotiation Advertisement (0x04) ....................................................................................... 28
6.2.6. Auto-Negotiation Link Partner Ability (0x05) .............................................................................. 30
6.2.7. Auto-Negotiation Expansion Register (0x06)................................................................................ 31
6.2.8. Auto-Negotiation NEXT Page Register (0x07) ............................................................................. 32
6.2.9. Auto-Negotiation Link Partner Received NEXT Page Register (0x08) ........................................ 32
6.2.10. MASTER-SLAVE control register (0x09) .................................................................................. 33
6.2.11. MASTER-SLAVE Status Register (0x0A).................................................................................. 34
6.2.12. MMD Access Control Register (0x0D) ....................................................................................... 35
6.2.13. MMD Access Data Register (0x0E) ............................................................................................ 35
6.2.14. Extended status register (0x0F) ................................................................................................... 35
6.2.15. PHY Specific Function Control Register (0x10) ......................................................................... 35
6.2.16. PHY Specific Status Register (0x11) ........................................................................................... 36
6.2.17. Interrupt Mask Register (0x12) .................................................................................................... 37
6.2.18. Interrupt Status Register (0x13) ................................................................................................... 38
6.2.19. Speed Auto Downgrade Control Register (0x14) ........................................................................ 38
6.2.20. Rx Error Counter Register (0x15)................................................................................................ 39
6.2.21. Extended Register's Address Offset Register (0x1E) .................................................................. 39
6.2.22. Extended Register's Data Register (0x1F) ................................................................................... 39
6.3. UTP MMD Register ................................................................................................................................. 39
6.3.1. PCS Control 1 Register (MMD3, 0x0) .......................................................................................... 39
6.3.2. PCS Status 1 Register (MMD3, 0x1) ............................................................................................. 40
6.3.3. EEE Control and Capability Register (MMD3, 0x14) ................................................................... 40
6.3.4. EEE Wake Error Counter (MMD3, 0x16) ..................................................................................... 40
6.3.5. Local Device EEE Ability (MMD7, 0x3C) ................................................................................... 40
6.3.6. Link Partner EEE Ability (MMD7, 0x3D) .................................................................................... 40
6.4. UTP LDS Register .................................................................................................................................... 41
6.4.1. LRE Control (0x00) ....................................................................................................................... 41
6.4.2. LRE Status (0x01) ......................................................................................................................... 41
6.4.3. PHY ID Register1 (0x02) .............................................................................................................. 42
6.4.4. PHY ID Register2 (0x03) .............................................................................................................. 42
6.4.5. LDS Auto-Negotiation Advertised Ability (0x04) ........................................................................ 42
6.4.6. LDS Link Partner Ability (0x07) ................................................................................................... 42
6.4.7. LDS Expansion (0x0A) ................................................................................................................. 43
