xilinx ultrascale ddr3控制器 开发手册

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xilinx ultrascale ddr3控制器 开发手册
R XILINX ALL PROGRAMMABLEn Performance 154 DIMM Configurations 166 Chapter 5: Design Flow Steps Customizing and Generating the Core 。171 O Planning∴∴ 180 Constraining the core Simulation,。,,,,,,,,,,,,。,,。,,,,,,,,,,,, ∴,,182 Synthesis and Implementation. Chapter 6: Example design Simulating the Example design Designs with Standard User Interface) 185 Project-Based Simulation ..186 Simulation Speed................ ············.:.·····.·· 194 Synplify pro black Box Testing.......................... 195 CLOCK DEDICATED ROUTE Constraints and bufg Instantiation 196 Chapter 7: Test bench Stimulus pattern ,..198 Bus Utilization∴…·… 199 Example patterns.,....... 200 Simulating the performance Traffic Generator ,,,,,,,,,.203 SECTION III: QDR ll+ SRAM Chapter 8: Overview Feature Summary.…… ,,,207 Licensing and ordering Information 207 Chapter 9: Product Specification Standards∴,,., ·..············ ..·..··..·..···.·.·:··.········: 209 Performance 209 Resource utilization 209 Port Descriptions 209 Chapter 10: Core Architecture Overview ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,211 PHY。,,,。 212 UltrascalearchitectureFpgAsMemoryipv1.1www.xilinx.com Send feedback PG150 November 18.2015 R XILINX ALL PROGRAMMABLEn Chapter 11: Designing with the Core Clocking.∴.……,…217 Resets,,,,,,,,,,,,,,,,,。,, ,∴......222 PCB Guidelines for QDR ll SRAM........ .222 Pin and Bank rules 222 Protocol Description 227 Chapter 12: Design Flow Steps Customizing and generating the core......,......... ,,,,。,,232 / O Planning∴. 237 Constraining the Core 237 Simulation,,,,,,,,,,,,,,,,,, 239 Synthesis and Implementation. Chapter 13: Example design Simulating the example design designs with Standard User Interface) 242 Project-Based Simulation 243 ulation Spee 254 Synplify pro black Box Testing 255 CLOCK DEDICATED ROUTE Constraints and bufg instantiation ,,,,,,,..,...256 hapter 14: Test Bench SeCtION V: RLDRAM 3 Chapter 15: Overview Feature summa 260 Licensing and Ordering Information........................ 261 Chapter 16: Product Specification Standards 262 Performance ,,,。,,,。,。,262 Resource utilization 262 Port Descriptions................. ,,262 Chapter 17: Core Architecture erview 264 Memory Controller 266 User interface allocation 266 UltrascalearchitectureFpgAsMemoryipv1.1www.xilinx.com Send feedback PG150 November 18.2015 R XILINX ALL PROGRAMMABLEn PHY 266 Chapter 18: Designing with the Core Clockin 270 Resets,,,,,,。,。,,,,,,,,, 275 PCB Guidelines for rldram 3 275 Pin and bank rules ..275 Protocol Description........................ 279 Chapter 19: Design Flow Steps Customizing and generating the core 288 1o Planning..... 293 Constraining the Core .293 Simulation,.,,,,,,,,,,,,,,,,,,,,,,,,,,,, 295 Synthesis and Implementation ,,∴∴,..295 Chapter 20: Example Design Simulating the Example Design(Designs with Standard User Interface) 298 Project-Based Simulation .... ,299 Simulation Speed.… 307 CLOCK DEDICATED ROUTE Constraints and bufg instantiation .......,.308 Chapter 21: Test Bench SECTION V: TRAFFIC GENERATOR Chapter 22: Traffic Generator Overview ,311 Simple traffic Generator 312 Advanced traffic Generator ,,,∴,...312 SeCtION VI: MULTIPLE IP CORES Chapter 23: Multiple IP Cores Creating a Design with Multiple IP Cores.....,..........,...... 336 Sharing of a bank........ ,,,,,,,..336 Sharing of Input Clock Source.................. 337 XSDB and dbg clk changes .337 MMCM Constraints 337 UltrascalearchitectureFpgAsMemoryipv1.1www.xilinx.com Send feedback PG150 November 18.2015 R XILINX ALL PROGRAMMABLEn SeCtION VI: DEBUGGING Chapter 24: Debugging FindingHelponXilinx.com n.339 Debug tools 341 Hardware Debug 346 seCtION VI: APPENDICES Appendix A: Migrating and Upgrading Appendix B: Additional Resources and Legal Notices Xilinx resources ,,,,,,,,,,,,,,,.520 References 520 Revision History.∴.∴∴∴∴∴∴∴ ,521 Please read: Important legal notices 532 UltrascalearchitectureFpgAsMemoryipv1.1www.xilinx.com Send feedback PG150 November 18.2015 XL|NⅩ ALL PROGRAMMABLE SECTION I: SUMMARY IP Facts UltrascalearchitectureFpgAsMemoryipv1.1www.xilinx.com Send feedback 7 PG150 November 18.2015 XL|NⅩ IP Facts ALL PROGRAMMABLE Introduction LogiCORE IP Facts Table Core Specifics The xilinx ultrascaletm architecture epgas Supported UltraScale+ TM Families Memory IP core is a combined pre-engineered Device Family() Virtex and Kintex UltraScale families controller and physical layer(PHY)for Supported user User interfacing UltraScale architecture FPGa user Interfaces designs to DDR3 and DDR4 SDRAM, QDR I+ See resource Utilization(DDR3/DDR4) SRAM, and rldram 3 devices Resources Resource Utilization( QDR Il+), Resource Utilization(Rldram 3) This product guide provides information about Provided with core using, customizing, and simulating a Design files RTL LogicoRETM IP ddR3 or DDR4 SDRAM, QDR II+ Example design Verilog SRAM, or a rldram 3 interface core for Test bench Verilog UltraScale architecture fpgas. it also describes Constraints file XDC the core architecture and provides details on Simulation customizing and interfacing to the core Model Not provided Supported N/A S/W Driver Features Tested Design Flows(2) Design Entry Vivado Design Suite For feature information on the ddr3/DDR4 Simulation (3) For supported simulators, see the Xilinx Design Tools: Release Notes guide SDRAM, QDR II+ SRAM, and RLdRAM 3 Inthesis interfaces, see the following sections Sy Vivado Synthesis Support Feature Summary in Chapter 1 for DDR3/ Provided by Xilinx at the Xilinx Support web page. DDR4 SDRAM Notes Feature Summary in Chapter 8 for QDR II+ 1. For a complete listing of supported devices, see the SRAM Vivado IP catalog 2. For the supported versions of the tools, see the Feature Summary in Chapter 15 Xilinx Design Tools: Release Notes guide RLDRAM 3 3. Behavioral simulations are only supported and netlist (post-synthesis and post-implementation)simulations are orted UltrascalearchitectureFpgAsMemoryipv1.1www.xilinx.com end seedlac PG150 November 18. 2015 Product Specification XL|NⅩ ALL PROGRAMMABLE SECTION II: DDR3/DDR4 Overview Product Specification Core architecture Designing with the Core Design flow steps Example design Test bench UltrascalearchitectureFpgAsMemoryipv1.1www.xilinx.com Send feedback PG150 November 18.2015 ⅩL|NX ALL PROGRAMMABLE Chapter 1 OverⅰeW The xilinx@ UltraScale TM architecture includes the DDR3/ DDR4 SDRAM cores. These cores provide solutions for interfacing with these SDRAM memory types. both a complete Memory Controller and a physical(Phy)layer only solution are supported. The UltraScale architecture for the DDR3/DDR4 cores are organized in the following high-level blocks Controller- The controller accepts burst transactions from the user interface and generates transactions to and from the sdram. the controller takes care of the sdram timing parameters and refresh. It coalesces write and read transactions to reduce the number of dead cycles involved in turning the bus around. the controller also reorders commands to improve the utilization of the data bus to the sdram Physical Layer- The physical layer provides a high -speed interface to the SDram. this ayer includes the hard blocks inside the fpga and the soft blocks calibration logic necessary to ensure optimal timing of the hard blocks interfacing to the SDRam The new hard blocks in the UltraScale architecture allow interface rates of up to 2,400 Mb/s to be achieved. The application logic is responsible for all SDRAM transactions, timing, and refresh. These hard blocks include Data serialization and transmission Data capture and deserialization High-speed clock generation and synchronization Coarse and fine delay elements per pin with voltage and temperature tracking The soft blocks include Memory Initialization-The calibration modules provide a JEDEC-compliant initialization routine for the particular memory type. the delays in the initialization process can be bypassed to speed up simulation time, if desired Calibration The calibration modules provide a complete method to set al delays in the hard blocks and soft ip to work with the memory interface. Each bit is individually trained and then combined to ensure optimal interface performance Results of the calibration process are available through the xilinx debug tools. After completion of calibration, the Phy layer presents raw interface to the sdram UltrascalearchitectureFpgAsMemoryipv1.1www.xilinx.com Send feedback 10 PG150 November 18.2015

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