xilinx 7serise DDR3控制器

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xilinx 7serise DDR3控制器
Date Version Revision 10/19/11 2 MIG 1.3 release. Updated ise design suite version to 13.3 Chapter 1: Added step 2 to MIG Output Options, page 14. Added note about optional use of the memory controller to Controller Options, page 17. Added arbitration scheme to AXIParameter Options, page 20 Added description of DCI Cascade under Figure 1-17. Updated text about devices with SSl technology and SLRs on page 25 and page 128 Changed error to tg_compare_error on page 27 Replaced Table 1-8. Added dr_wr_cmd_o, vio_fixed_instr_value, vio_fixed_bl_value, vio_pause_traffic, and vio_data_mask_gen signals to Table 1-13. Added signals to the User Interface in Figure 1-31 and Figure 1-33. Added app_sr_reg, app_sr__active, app_ref_req. app_ref_ack, app_zq_req, and app_zq_ack signals to Table 1-17. Added app_wdf_rdy, app_ref_req, app_ref_ack, app_zq_req, app_zq_ack, Read Priority with Starve Limit(rD_PRI REG STaRvE_ LIMIT), Native Interface Maintenance Command signals, User Refresh, and User ZQ sections Added C_RD_WR- ARB- ALGORITHM to Table 1-19. Updated fields in Table 1-29, changed Hi Index(Rank )to Rank Count, and added CAS slot field. Updated AXI Addressing and Physical Layer Interface(Non-Memory Controller Design). Added Figure 1-57 through Figure 1-59 in Write Path In Table 1-36, removed DISABLED option from RTT_NOM for DDR3_ SDRAM, changed RTT_NOM to RTT_WR in RIT_WR updated SIM_ BYPASs_INIT_CAL, and updated table note 2. In Table 1-37, updated tzQI and added USER_REFRESH Added Table 1-38. In Configuration, updated constraints example and removed paragraph about SCL and SDA Chapter 2: Added step 2 to MIG Output Options, page 164. Added Input Clock Period description in Controller Options, page 167. Added Debug Signals Control and Internal Vref Selection options to FPGA Options, page 170 Added i/O Planning Options, page 172 In System Pins Selection, page 175, changed cal_done signal to init_calib_complete and error signal to tg_compare_error. Replaced Table 2-2 Changed file names in Table 2-8. Updated signal names in Figure 2-23, Figure 2-24, and figure 2-25 Updated signal names in Table 2-10 Added CPT_CLK_CQ_only and updated value for SIM_ BYPASS_INIT_CAL in Table 2-13. Added Table 2-14 Updated pinout rules in Pinout Requirements, page 204. Added paragraph about DCI and IN-TERM after Table 2-15. Added Debugging dril+ sram designs, page 207 Chapter 3: Added step 2 to MIG Output Options, page 232. Added Input Clock Period description in Controller Options. Added Debug Signals Control and Internal Vref Selection options to FPGA Options, page 237 In System Pins Selection, changed cal_done signal to init_calib_complete and error signal to tg_compare_error Changed file names in Table 3-8 Removed Table 3-12, which contained reserved signals not used. Added rst phaser ref to Table 3-12. Removed Phy-Only Interface section. In Table 3-15, added rld ADDR Width, mem TYPe CLKin PERiOD, and SIMULATION, and renamed CLKFBOUT MULt, CLKOUTo diVide CLKOUTl_DIVIDE, CLKOUT2_DIVIDE, and ClKout3_DIVIDE. Updated Table 3-16. Added paragraph about dCI and IN_ TERM after Table 3-27 Added Chapter 4, Multicontroller Design UG586June13.2012 www.xilinx.com 7 Series FPGAs Memory Interface Solutions Date Version Revision 01/18/12 1.3 MIG 1.4 release. Updated ISE Design Suite version to 13. 4. Updated GUI screen captures throughout document Chapter 1: Added support for DDR2 SDRAM. Added option 3 to MIG Output Options Added EDK Clocking. Updated Simulation Considerations. Added Replaced Figure 1-26 and Figure 1-50 Chapter 2: Removed Input Clock Period option from Controller Options Added Memory Options. Added Reference Clock option to FPGA Options. Updated Debug gnals Chapter 3: Removed Input Clock Period option from Controller Options. Added Input Clock period option to memory options added reference clock option to FPGA Options Added Debugging RLDRAM I Designs 04/24/12 14 MIG 1.5 release. Updated IsE Design Suite version to 14.1. Updated GUIscreen captures throughout document. Replaced iodelayctrl with idelayctrl throughout Chapter 1: Added I/ O Power Reduction option to FPGA Options. Revised I/O standards for sys_rst option in Bank Selection. Added Creating Ise Project Navigator Flow for MIG Example Design, Power-Saving Features, Multi-Purpose Register Read Leveling, OCLKDELAYED Calibration, Upsizing and Downsizing, and External vref sections Changed bits[16: 15 to from Rank Count to Reserved in the PHY Control word. Revised maximum setting of NUM_DQ_ PINS in Table 1-11. Revised Figure 1-37 flowchart Removed Ranksel[1: 0] from Figure 1-38 and Figure 1-40 Added mc_odt and mc_cke to Table 1-31. Replaced AXI Addressing. Updated REFCLK_ FREQ, RANK_ WIDTH, and WRLVL in Table 1-36. Added DATA_IO__PRIM_TYPE to Table 1-37. Added bullet about dQsCc pins to Bank and Pin Selection Guides for DDR3 Designs Changed DIFF_SsTL_15 to DIFF-SSTL18_I and ssti15 to ssti18Ⅲ Chapter 2 Changed DIFF- SSTL_15 to DIFF- HSTL I and sstL15 to HsTL I Revised 1/O standards for sys_rst option in System Pins Selection. Revised the PHY_ BITLANE parameters in Table 2-14. Added System Clock, PLL Location and Constraints and Configuration sections Chapter 3: Changed DIFF Sstl 15 to DIFF HSTL I and sstL15 to HSTL _I to Revised I/O standards for sys_rst option in System Pins Selection. Added the Write Calibration, System Clock, PLL Location, and Constraints, and Configuration sections. Revised the PhY bitlane parameters in Table 3-16. In Table 3-30, added dbg-wrcal_sel_stgl 1: 01, dbg_wrcal[63: 0 l, dbg_wrcal_done[2: 01 dbg_wrcal_po_first_edge [5: 0), dbg_wrcal_po_second_edge[5: 0, and dbg_wrcal-po_final[ 5: 01 06/13/12 15 Revised the recommended total electrical delay on CK/CK# relative to dQS/dQS# on Page 133 7 Series FPGAs Memory Interface Solutions www.xilinx.com UG586June13,2012 Table of contents Revision history Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution Introduction Features.… 7 Getting Started with the CORE Generator Tool Getting Started with EDK Simulation considerations 55 Core△ rchitecture 55 Designing with the Core .104 Interfacing to the Core Customizing the Core 118 Design guidelines 127 Debugging dDR3 designs 4 Supported Devices for 7 Series FPGAs 155 Chapter 2: QDRIl+ Memory Interface Solution Introduction ...157 Getting Started with the CORE Generator Tool 157 Core architecture ··· 184 Customizing the core 199 Design Guidelines 204 Debugging QDRI轩+ SRAM Designs.……… 207 Chapter 3: RLDRAM II Memory Interface Solution Introduction Getting Started with the CORE Generator Tool ,,,225 Core Architecture 254 Customizing the Core ,270 Design guidelines Debugging RLDRAM II Designs ........285 Chapter 4: Multicontroller Design Introduction Getting Started with the CORE Generator Tool 309 MIG Directory Structure.………… b·鲁··D 314 7 Series FPGAs Memory Interface Solutions www.xilinx.com 5 UG586June13.2012 E XILINX Appendix A: Additional Resources Xilinx Resources Solution centers 315 R eferences “ www.xilinx.com 7 Series FPGAs Memory Interface Solutions UG586June13,2012 E XILINX Chapter 1 DDR3 and DDR2 SDRAM Memory Interface Solution Introduction The Xilinx( 7 scries FPGAs memory interface solutions core is a combincd pre-cnginccred controller and physical layer(PHY) for interfacing 7 series FPGA user designs and AMBA advanced extensible interface(AXI4)slave interfaces to ddR3 and ddri SDRAM devices. This user guide provides information about using customizing, and simulating a LogiCORE TM IP DDR3 or DDR2 SDRAM memory interface core for 7 serie FPGAS. In the Embedded Development Kit (EDK)this core is provided through the Xilinx Platform Studio(XPS)as the axi_7series_ddrx ip with a static AXIA to ddR3 or DDr2 SDRAM architecture. The user guide describes the core architecture and provides details on customizing and interfacing to the core Features Enhancements to the Xilinx 7 series FPGa memory interface solutions from earlier memory interface solution device families include Higher performance New hardware blocks used in the physical layer: PHASER IN and PHASER_OUT, PHY control block, and I/O FIFOs (see Core Architecture, page 55) Pinout rules changed due to the hardware blocks(see Design Guidelines, page 127) Controller and user interface operate at 1/4th the memory clock frequency. Getting Started with the CORE Generator Tool This section is a step-by-step guide for using the CORE Generator M tool to generate a DDR3 or DDR2 SDRAM memory interface in a 7 series FPGA, run the design through implementation with the Xilinx tools, and simulate the example design using the synthesizable test bench provided System Requirements ISEB Design Suite, v14.1 7 Series FPGAs Memory Interface Solutions www.xilinx.com UG586June13.2012 Chapter 1: DDR3 and ddr2 SDRAM Memory Interface Solution E XILINX Customizing and generating the core Generation through Graphical User Interface The Memory Interface Generator(MIG) is a self-explanatory wizard tool that can be invoked under the COre generator tool from XPS. This section is intended to help in understanding the various steps involved in using the mig tool These steps should be followed to generate a 7 series FPGA DDR3 SDRAM design(most MIG options are same between ddR3 and DDR2 SDRAM interfaces) Note: The exact behavior of the Mig tool and the appearance of some pages/options might differ depending on whether the MIG tool is invoked trom the CORE Generator tool or from XPS, and whether or not an aXi interface is selected. these differences are described in the steps below 1. To invoke the MIg tool from XPS, Select Memory and Memory Controller> AXI 7 Series Memory Controller from the XPS IP catalog(when adding new ip to the system)or right-click the axi_7series_ddrx component in the XPS System Assembly View and select Configure IP.. Then skip to MIG Output Options, page 14 Otherwise, to launch the mig tool from the core generator tool, type mig in the search IP catalog box(Figure 1-1) Xilinx CORE Generator- No Project 包回区 File View Manage IP Help b日国0面 CORE Gener ator Hap K:? IP Catalog x View by Function View by Name A lagi CkRE Xilinx CORE Generator Name B-D Memories Storage Elements 多‖② Memory Interface Generators There is no project open. 出MG 3.5 田MG 出MG AX14 Copyright (c)1995-2010 Xilinx, Inc. All rights reserved Console CoreGen has been configured with the following Xilinx repositories J:\0.39.0lcoregent'[xil_index xml] The IP Catalog has been reload Search IP Catalog: mig Clear Search console [Save gear 日 IP versons D ony P compatbe with chose pat Informaion a Warings Errors Part: Unset Design Entry: Unset Figure 1-1: Xilinx CORE Generator Tool www.xilinx.com 7 Series FPGAs Memory Interface Solutions UG586June13,2012 E XILINX Getting Started with the CORE Generator Tool 2. Choose File> New Project to open the New Project dialog box. Create a new project named 7Scrics_MIG_Example_Design(Figure 1-2) ■ ew Project Ctrl+N B Open Project Ctrl+O Close Project Ctrl+W Re 日S Ctrl+s 目 Preferences Exit uG586c102091410 Figure 1-2: New coRE Generator Tool project 3. Enter a project name and location. Click Save(Figure 1-3) New Pro ject p区 Save jn:O Coregen 国伴图 My recent Documents Desktop My D acumen My Computer My Network File name 3 design. cgp Save Places Save as tupe: xilinx CORE Generator Project File ( cgp)-Cancel UG586c1_03_11101 Figure 1-3: New Project Menu 4. Select these project options for the part( figure 1-4 Select the target KintexTM-7or Virtex@-7 de 7 Series FPGAs Memory Interface Solutions www.xilinx.com UG586June13.2012 Chapter 1: DDR3 and ddr2 SDRAM Memory Interface Solution E XILINX roject Options 区 Generation Advanced Select the part for your project Kintex 7k410t ackageFbg676 Apply UG586c10410610 igure 1-4: CORE Generator Tool Device Selection Page 10 www.xilinx.com 7 Series FPGAs Memory Interface Solutions UG586June13,2012

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