UltraScale Architecture Memory Resources 2
UG573 (v1.13) September 24, 2021 www.xilinx.com
Revision History
The following table shows the revision history for this document.
Date Version Revision
09/24/2021 1.13 Revised WE description in Address Collision. Revised Block RAM ECC VHDL and
Verilog Templates. Added UG901 to References.
03/17/2021 1.12 Added additional bullet to list before Table 1-3 . Revised values, default, and type
for IS_XX_INVERTED attributes in Tab le 2- 5.
08/18/2020 1.11 Revised important notes in Block RAM Summary, Common-Clock/Single-Clock
FIFO, and Block RAM and UltraRAM Differences.
02/04/2019 1.10 Added information on common and independent clocks in Address Collision.
Revised port A to write port and port B to read port in Simple Dual-Port Block RAM.
Removed content clear from UltraRAM Key Features.
02/09/2018 1.9 Revised description for EN_A and EN_B ports in Tab le 2- 2. Revised Figure 2-16.
11/14/2017 1.8 Revised important note in Common-Clock/Single-Clock FIFO and added note to Set
Enable Auto Sleep Mode – EN_AUTO_SLEEP_MODE. Revised UltraRAM Summary.
Removed Figure 2-28 and associated verbiage.
08/10/2017 1.7 Added important note to Common-Clock/Single-Clock FIFO. Revised ECC
Encode-Only Read.
05/04/2017 1.6 Updated Tabl e 2-5.
03/15/2017 1.5 Revised important note in Block RAM Summary. Added note 2 to Ta ble 1- 16.
Revised Reset – RST_A, RST_B. Added UltraRAM Timing Diagrams.
07/20/2016 1.4 Revised Differences from Previous Generations, Synchronous Dual-Port and
Single-Port RAMs, Power Saving – RDADDRCHANGE[A|B], Power Gating Enable
Input – SLEEP, Data-Out Buses – DOUT_A, DOUT_B, Read Status Output –
RDACCESS_A, RDACCESS_B, Optional Cascade Register Stage – REG_CAS_[A|B],
Cascading UltraRAM and Matrix Configurations, and Cascade User Attributes.
Added note to Tabl e 1-1 6 and Tab le 1-3 2. Updated Tab l e 2-5 . Added
AVG_CONS_INACTIVE_CYCLES, MATRIX_ID, NUM_URAM_IN_MATRIX, and
NUM_UNIQUE_SELF_ADDR_A|B Attributes. Updated Figure 2-1 and Figure 2-5.
11/24/2015 1.3 Added UltraScale+ device information. Updated Introduction to the UltraScale
Architecture to include UltraScale+ information. Updated important note in
Block RAM Summary. Added introductory paragraph to RAMB18/36 Unused Inputs.
Reorganized user guide by incorporating previous Chapter 2 (Built-in FIFO) and
Chapter 3 (Built-in Error Correction) into Chapter 1, Block RAM Resources, and
adding a new Chapter 2, UltraRAM Resources.
02/24/2015 1.2 Updated Content Initialization – INIT_xx.
