Xilinx高端FPGAPCIE3.0IP分析

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XILINX高端开发的必备资料,对PCIE IP有详细的深入分析
<zseries Integrated Block for PCI ExDIeS AXl4-Stream Incuded xilinx ip pcie_7x33 9-EXIBridge for PCI Express Gen3 Subsafe AX4. AX4-Stream ncludedxilirx.comipaxipcie3:3.0 受 Memory Mapped To PCI Expr8s AX4 ncluded xilinx com.ip axi_pcie. 2.8 9TMEndge Subsystem for PCl Express Ecte) AXi4 AXi4-Stream Induded xilinx comip xoma 40 安 PCle PHY IP Included xilinx.:ip:pcie_phy:1.0 F Uitrascale+ PCI Express 4c integrated Block AX14. AXIA-Stream xilinx. com p. pcie4c uscale plus: 1.0 F UitraScale+ PCI Express Integrated Block AX4-strearm ncluded xilinx commi pcie_ uscale_plus: 1.3 y Uitrascale FPGA Gen3 Integrated Block for PCl Express AX14-Stream Includedxilinx.comip:pcle3_ultrascale:4.4 2viritex-7 FPGA Gen3 Integrated Block for PCI Express Included xilinx comip: pcie_7x43 3器件选型 对于刈lnx公司提供的PCEP核,相比于其它的高速串行设备,其有个显著的特点, PCE护P核所包含的高速串行核是专门定制的,不能给通过配置和其它的高速串行设备共 享。所以很多用户会发现,虽然使用的FPGA器件支持高速串行接口|P,但是不能够将其 扩展,变成支持的PCE高速串行接口|P。这一点在具体的器件选型的时候要特别注意,避 免不必要的损失。下面以 Zyng UltraScale+系列具体分析一下相关的器件选型。 如下图所示为 Zyng UltraScale+CG系列所支持的所有的FPGA器件型号,我们发现有 个PC| Express Gen3x16的条目,这里只有zU4CG/zU5CG/zU7CG这三个FPGA具体的 型号有支持。 Zynq@ UltraScale+ TM MPSoCs: CG Devices Device Name)ZU2CG ZU3CG ZU4CGZU5CG ZU6CG ZU7CG U9CG Application Processor Core Dual-core ARM Cortex M-A53 MPCore" up to 1.3GHz Processor Unit Memory w/ECC L1 Cache 32KB l/D per core, L2 Cache 1MB, on-chip Memory 256KB a Real-Time Processor Core Dual-core ARM Cortex-R5 MPCore up to 533MHz 手 Processor Unit Memory w/ECC L1 Cache 32KB l/D per core, Tightly Coupled Memory 128KB per core External Memory Dynamic Memory Interface x 32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 with ECC Static Memory Interfaces NAND, 2x Quad-SPl s Connectivity High-Speed Connectivity PCle"Gen2 x4, 2x USB30, SATA 3.1, Display Port, 4x Tri-mode Gigabit Ethernet General Connectivity 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x 12C, 2x SPL, 4x 32b GPIO Integrated Block Power Management Full Low /PL/Battery Power Domains Security RSA, AES and SHA AMS-System Monitor 10-bit, 1MSPS-Temperature and voltage Monitor PS to PL Interface 12 x 32/64/128b AXI Ports System Logic Cells(K Programmable CLB Flip-Flops (K 141 176 234 Functionality 461 CLB LUTs( K) 47 71 117 230 274 Max Distributed RAM(Mb) 1.2 3.5 6.9 Total Block RAM(Mb) 5.3 7.6 4.5 5.1 25.1 110 32.1 UltraRAM (Mb) 13.5 180 270 Clocking Clock Management Tiles(CMTs) DSP Slices 240 360728 1,248 1,973 1728 2.520 PCI Express Gen 3x16/ Gen4x8 Integrated IP 150G Interlaken 我们通过Ⅵvado工程做相关的实验,当将FPGA的器件选择为ⅩCzU9CG-FFC900 2-,发现在 IP Catalog界面,搜索PCE支持的|P,所有的|P都是灰色,提示器件不兼 容。即使是 AXI Memory Mapped这种只支持PClE20的|P都是不能够工作的。考虑到 FPGA速度等级的影响,将器件换成XCzU9CG-FVC900-2-E,或者XCzU9CG-FVC900 2L∨-E等其它XCzU9CG的器件,其结果也是一样的,均不支持PCE相关的|P。对于该型 号的PPGA产品,要支持PC功能,唯一可以使用的只能是 ZYNQ PS内部的PCE20X4这 个硬校 Search: Q- pci 3(7 matches) F 7 Series Integrated Block for PCI Express F AXI Bridge for PCI Express Gen3 Subsystem FF AXI Memory Mapped To PCI Express F DMABridge Subsystem for PCl Express(PCle) F UltraScale+ PCI Express Integrated Block x Ultrascale FPGA Gen3 Integrated Block for P. F Vintex-7 FPGA Gen3 Integrated Block for PCI E. ENTER to select EsC to cancel ctrl+Q for IP details 当将器件选择为zU5CG-bvb900-2∨-e这个器件型号的时候,发现在| p Catalog界 面,搜索PCIE支持的|P,发现支持DMA的|P以及支持单独的PCIE的 steam接口的|P都 是高亮状态,即其除了支持 ZYNQ PS内部的PC!E内核,还允许在PL端支持PCE30的功 能。 E 7 Senes Integrated Block for PCI Express AX14- Stream ncluded xilinx com ip pcie 7x33 f AXI Bridge for PCI Express Gen3 Subsystem AX14, AX14-Stream Includedxilinx.comip:axi_pcie3.3.0 F AXI Memory Mapped To PCl Express AX14 Included xilinx com ip: axi_pcie: 2.8 E DMA/Bridge Subsystem for PCI Express(PCle) XI4, AXI4-Stream Pre-Production Included xilinx com ip dma: 4.0 R PCle PHY IP Included xilinx. com ip: pcie_phy.1.0 F UltraScale+ PCI Express 4c Integrated Block AXI4 AX 4-Stream Included xilinx comip pcie4c_uscale_plus 1.0 E Ultra Scale+ PCI Express Integrated Block AXI4-Stream Pre-Production Included xilinx com ip: pcie 4_uscale_plus:1.3 F Ultra Scale FPGA Gen3 Integrated Block for PCI Express AXI4-Stream Included xilinx. com ip pcie 3_ultrascale: 4.4 p Virtex-7 FPGA Gen3 Integrated Block for PCI Express AXI4-Stream Included xilinx comip pcie37x43 当将器件选择为四UcG/乙U5CG,即使是1-e的版本都能够支持DMA的模式,但是 DMA模式下,只能配置为印P模式。不能配置为root模式。如果是AⅪ- Bridge的模式,则 都支持 Root Complex和EP两种情况。 如下图所示:为 Zyng UltraScale+EG系列所支持的所有的FPGA器件型号,我们发现有 一个PC| Express Gen3x16的条目,对于低端产品其仍然只有zU4EG/zU5EG/ZU7EG这三个 FPGA具体的型号有支持 Device NameL ZU2EG ZUBEG ZU4EG ZUSEG ZUGEG ZUZEG ZUSEG ZU11EG ZU15EG ZU1ZEG ZU19EG ation Quad-core ARM Cortex'M-A53 MPCore m up to 1.5GHz Processor unit Memory w/ECC L1 Cache 32KB l/D per core, L2 Cache 1MB, on-chip mi 256KB eal-Time Processor Core Dual-core ARM Cortex- R5 MPCore M up to 600MHz Memory w/ECC L1 Cache 3 2KB l/D pcr corc, Tightly Coupled Memory 128KB pcr corc Graphics Processing Unit Mali-400 MP2 up to 667MHZ L2 Cache 64KB 2 External Memory ynamic Memory Interface 32/x64:DDR4,LPDDR4,DDR3,DDR3LLPDDR3with ECC Static Memory Interfaces NAND, 2x Quad-SPl High-Speed Connectivity PCle'Gen2 x4, 2x USB3.0, SATA3.1, DisplayPort 4x Tri-mode Gigabit Ethernet General Connectivity 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x 12C, 2x SPL, 4x 32b GPIO Intcgrated Block Full/Low/ PL/Battery Power Domains AMs- Systcm Monito 10-bit, IMSPS- Temperature and voltage Monitor Ps to PL Interfaco 12X32/64/128bAXP System Logic Cells(( K) 103 154 192 256 469 504 60 653 747 9261,143 rogrammable CLB Flp Flops(K) 34429 597 8471.045 CLB LUTs(K)4n18811721523027429934142523 Max Distributed RAM (Mb) 1.2 1.8 2.6 3 6,2 9.1 138.09.8 Memory Total Block RAM(Mb) 5.3 7.6 4.5 5.1 25.1 11.0 21126.2280346 UItraRAM(Mb) 13.518.0 0 22531.528.736.0 nt Tiles(CMTs) 33 444 8 360728124819731,7282.522929352815901968 Cl Express@ Gen 3x16/ Gen4xB 而对于Ⅺlinκ公司提供的zCU102开发板,其提供的核心器件为ZU9EG,而这个系列 的FPGA是不支持。当将器件选择为z∪9EG-fbwb900-2∨-e这个器件型号的时候,发现在 IP Catalog界面,搜索PCE支持的P,发现PC!ePHY|P这个|P是支持可配置的,其它所 有的PCEP都是不支持的。在zCU102开发板上面PL端要进行PC|30的开发,该开发板 是不支持的。 e PCI Express fF 7 Series Integrated Block for PCI Express AXI4-Stream Included xilinx com ip pcie 7x33 F AX Bridge for PCl Express Gen3 Subsystem AX14. AX 4-stream Included xilinx com. ip: axi pcie: 3.0 FF AXI Memory Mapped To PCI Express Included xilinx com ip axi paie: 2.8 F DMA/Bridge Subsystem for PCI Express(PCle AX14 AXl4-Stream Included xilinx com: ip dma: 4.0 F PCle PHY IP ProductionIncludedxilinx.com.ip.pcie_phy.1.0 F UItra Scale+ PCI Express 4c Integrated Block AX4 AX14-Stream Included xilinx com:ip: pcie4c_uscale_plus: 1.0 H UItrascale+ PCI Express Integrated Block A④4 Stream Included xilinx com: ip: pcie uscale plus: 1.3 F UItraScale FPGA Gen3 Integrated Block for PCI Express AXI4-Stream Included xilinx com ip pcie ultras cale. 4.4 p Virtex-7 FPGA Gen3 Integrated Block for PCI Express AXI4-Stream Included xilinx com ip: pcie 7x: 4.3

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