xilinx sparten6 ddr3 开发手册
xilinx sparten6 ddr3 开发手册.pdf
12/02/09 2.0 Moved Chapter 3, " Gctting Started, "and Chapter 6, Debugging MCB Designs, "and to UG416, Spartan-6 FPGA Memory Interface solutions user guide Changed introduction in About This guide, page 7 hapter 1 Revised Note 1 in Table 1-1, page 12 to refer to the data sheet for specific values Added note 2 to Table 1-2, page 13 Chapter 2 In Table 2-3, changed the description and values of the C MC Calibration MODE attribute on pagc 25 Appended two sentences to exception(a)on page 30 hapter 3 Replaced text regarding the speed of the calibration clock, calib_clk, on page 39 Chapter 4: Rephrased note l under Figure 4-1, page 46 In the third paragraph after the notes on page 46, removed the sentence about libration logic Added note after first paragraph of Calibration, page 47 Removed portion of sentence about calibration logic in first paragraph of Phase 2 DQS Centering, page 48 Added paragraph above Figure 4-13, page 59 Added note on page 62 before Table 4-5 01/05/10 2.0.1 Revised document hyperlinks 03/04/10 2.1 Chapter 1: In the Fcatures and Bencfits scction, added bullet for input termination automatic calibration to section. In Table 1-1, added parameters in Dala Rale minimum column and updated table note 2 In Table 1-2, revised table note 1 Chapter 2: In Table 2-2, addedTIIREEQUARTERS"as a possible value for the Memory Drive Strength attribute, and modified the description for Memory Burst Length attribute, indicating that ddr3 is always set to 8. In the clock reset, and calibration Signals section, added calibration to the heading name, introductory text, and caption of Table 2-4 In Table 2-4, changed the signal name BUFPLL to BUFPLL-_MCB, changed the signal name sys_ rst to async_rst, and added signals mcb_drp_clk and calib_done. In the Memory Device Interface section, modified descriptive text related to rzG and zio pins Added clarifying text in Note(page 30)relating to unused pins from an active MCB reverting to general-purpose I/O In Table 2-9, modified descriptions for the rzq and zio sIgna Chapter 3: In Table 3-1, removed memory devices mt41K128M8XX-25 and MTA1K256M4XX-25. In the Clocking section, added text related to MiG/ EDK generation of clocking infrastructure. Clarified lext related lo location of externally driven PlL Revised text related to calibration clock In figure 3-3, changed signal name from calib clk to mcb drp clk Changed the end of the first sentence after figure 3-3 Changed the first sentence about the calibration related clock on page 39. Under Figure 3-4, added clarifying text related to using bankl MCB pins as BPi pins. In the Additional Board Design Requirements section on page 43, clarified requirements for pull-down resistors on the rESeT, CKe, and ODT signals. Added simultaneous Switching output Considerations section Chapter 4: In the Phase 1: Input Termination section, added clarifying text related to input termination of the RzQ and zio pins. In the Addressing section, added clarifying text related to offsetting the starting address location using the write data mask inputs Added the Read Latency and Suspend sections Appendix A: Updated JEDEC URLS 06/14/10 2.2 XCN10024, MCB Performance and TAG Revision Code for Spartan-6LX16 and LX45 FPGAs, addresses these changes Chapter 1: Added an important notc about Standard and Extended pcrformance modcs Chapter 2: In Table 2-4, included the BUFPLL MCB block name in the pll_lock description and changed the clock frequency example in the sysclk_2x description Chapter 3: In Clocking, removed LOCKED and pll_lock from the Pll block and MiG Wrapper blocks, respectively, and changed the clock frcqucncy cxamples in the sccond and fourth paragraphs under Figure 3-3 on page 38 08/09/10 2.3 Chapter 1: In Table 1-1, changed the minimum data rate value for Lpddr and indicated that -3N speed-grade devices do not support the MCB in table note 1. Added table note Chapter 2: In Table 2-4, added italicized sentence to the calib_done signal description. In Table 2-5, Table 2-6, and Table 2-7, added sentence about reset being required to recover to the px-cmd -error,pxwr_error, and pX_rd_error descriptions, respectively Chapter 3: Added BUFG in Figure 3-3. Added sentences about preferred PLL location to the end of the first paragraph under Figure 3-3. Added sentences about driving mCbs on both sides of the device to the end of the second paragraph under figure 3-3. Added Modifying the Clock Setup section Added fourth bullet about VREF to Additional Board Design Requirements Chapter 4: In the second to the last paragraph of phase 1: Input Termination, replaced sentence about VREF source still being provided for different I/O standards when a calibrated input termination is desired with sentence about lpddr memory not requiring VreF Added sentence about resulting input termination to the last paragraph of Phase 1: Input Termination on page 47 Appendix A: Removed obsolete link Table of Contents Revision History Guide Contents Additional Documentation 7 Additional Support resources cope Introduction Features and Benefits Block diagram ........10 Performance ,,12 Device Family Suppe 13 Supported Memory Configurations 14 Software and Tool Support 14 Architecture Overview 15 Port Configurations ing a Port configuratio 18 arbitratio Programmability 20 Interface Detail 25 User(Fabric Side) Interfa 25 Clock, Reset, and Calibration Signals.………∴… Command path 6 Write Datapath 27 Read datapath ····.···· 28 Self-Refresh signals Memory device interface 30 Design Flow CORE Generator Tool ..34 Supported Memory Devices .,35 Simulatie 36 Resource utilization 37 Clocki g 37 Modifying the clock se 39 &A XILINX Migration and Banking 40 PCB Layout Considerations General Guidelines 41 Data, Data Mask and Data Strobe guidelines ,,42 Address, Control, and clock guidelines ····· 42 Additional board design requirements 42 Simultancous Switching Output Considerations 43 Startup Sequence ··· .45 Calibration 47 Phase 1: Input Termination 47 Phase 2: DQS Centering 48 Phase 3: Continuous DQS Tuning 48 Instructions 50 Addressing Command Path Timing 52 Write Path Timing .,53 Read Path Timing 54 Memory transactions imple write Simple read .56 Read Latency. 57 Self refresh 58 Suspend Suspend mode without dRaM Data Retention Suspend mode with dram data Retention Additional Suspend mode requirements 61 Byte Address to Memory Address Conversion ...,,61 Transaction Ordering and Coherency 64 Memory Standards.…, .........,,65 PCB Layout and Signal Integrity ,,,,,,65 &A XILINX Preface about This guide This document describes the Spartan-6 FPGAmemory controller block(MCB). Complete and up-to-date documentation of the Spartan-6 family of FPgas is available on the xilinx websiteathttp://www.xilinx.com/products/spartan6/index.htm To implement an MCB based memory interface, one of the two supported design tool flows must be followed 1. Memory Interface Generator(MIG For traditional (non-embedded) FPGA designs, refer to UG416, Spartan-6 FPGA Memory Interface Solutions user Guide for information on implementing an MCB based memory interface using the MiG tool within the CORE GeneratorTM software. This document also contains information on debugging McB interfaces 2. Embedded Development Kit(eDK) For embedded designs, refer to dS643 multi-Port memory controller (mpmc ) for details on how the mcb is used to implement the mPmc within the edK environment This manual contains the following chapters Chapter 1, Memory Controller Block Overview, introduces the Spartan-6 FPGA MCB Chapter 2, MCB Functional Description, describes the architecture, signal interface, and possible configurations of the mcB Chapter 3, Designing with the mCB, provides details on how to incorporate the mcb into a Spartan-6 design, with specifics on how to customize the block for a given application Chapter 4, MCB Operation, explains how the mcb functions in various operational modes: startup, calibration, refresh, precharge, standard read write transactions, etc nhe pendix A, References, contains links to additional documentation relevant to emory interface design The following documents are also available for download at http://www.xilinx.com/products/spartan6/index.htm partan-6 Family overview This overview outlines the features and product selection of the Spartan-6 family &A XILINX partan-6 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the partan-6 family Spartan-6 FPGA Packaging and Pinouts Product Specification This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications Spartan-6 FPGA Configuration User Guide This all-encompassing configuration guide includes chapters on configuration interfaces(serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and jTAG configuration, and reconfiguration techniques Spartan-6 FPGA SelectIO Resources User Guide This guide describes the SelectIOTM resources available in all Spartan-6 devices Spartan-6 FPGa Clocking resources User guide This guide describes the clocking resources available in all Spartan-6 devices, including the dCMs and the Plls partan 6 FPGA Block RAM Resources User Guide This guide describes the Spartan-6 device block RAM capabilities partan-6 FPGA Configurable logic block User guide This guide describes the capabilities of the configurable logic blocks(clbs available in all spartan-6 devices Spartan-6 FPGA GTP Transceivers User Guide This guide describes the gtp transceivers available in Spartan-6 LXT FPGAs partan-6 FPGA DSP48A1 Slice User Guide This guide describes the architecture of the DSP48Al slice in Spartan-6 FPGAs and provides configuration examples partan-6 FPGA PCB and Pin Planning Design Guide This guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface level Spartan-6 FPGA Power Management User Guide This guide provides information on the various hardware methods of power management in Spartan-6 devices, primarily focusing on the suspend mode To find additional documentation see the Xilinx website at http://www.xilinx.com/support/documentation/index.htm To search the Answer Database of silicon, software, and ip questions and answers or to create a technical support WebCase, see the Xilinx website at http://www.xilinx.com/support &A XILINX Chapter 1 Memory Controller block overview This chapter provides an overview of the Spartan(B-6 FPGA memory controller block (MCB). It contain Introduction Features and benefits Block Diagram Performance ce Family support Supported Memory Configurations Software and Tool su The mCB is a dedicated embedded block multi-port memory controller that greatly simplifies the task of interfacing Spartan-6 devices to the most popular memory standards The mCB provides significantly higher performance, reduced power consumption, and faster development times than equivalent Ip implementations. The embedded block implementation of the MCB conserves valuable FPGa resources and allows the user to focus on the more unique features of the FpGa design The key features and benefits of the spartan-6 FPGA memory controller block are DDR, DDR2, DDR3, and LPDDr ( Mobile DDr) memory standards support Up to 800 Mb/s(400 MHz double data rate) performance Up to four MCB cores in a single Spartan-6 device. Each MCB core supports 4-bit, 8-bit, or 16-bit single component memory interfacc Memory densities up to 4 Gb p to 12.8 Gb/s aggregate bandwidth Configurable dedicated multi-port user interface to FPGA logic 1 to 6 ports per MCB depending on configuration 32-,64-,or 128-bit data bus options Bidirectional(r/W)or unidirectional (W only or r only) port options &A XILINX Memory Bank management Up to eight memory banks open simultaneously for greater controller efficiency Embedded controller and physical interface(PHY), providing Predictable timing Low power P Guaranteed performance Predefined pinouts (I/o locations) for each MCB Simplified board design Predefined I/Os not used in an MCB interface become general-purpose I/Os(see page 30 for details) Common memory device options and attributes support Programmable drive strength On-Die Termination (ODT CAS latency Self refresh(including partial array) · Refresh interval Write recovery time Automatic delay calibration of memory strobe and read data inputs Adjusts DQS (strobe)to DQ(data) timing relationship for optimal read performance Optional automatic calibration of FPGA on-chip input termination for optimal signal ntegrity Supported by Xilinx COrE Generator and Embedded Development Kit(EDk) design tools Memory Interface Generator (MiG)tool within the COre Generator software simplifies the mcb design flow Embedded designs can also access the mcb via the multi-port memory controller (MPMC)IP in the edk tool The block diagram in Figure 1-1 shows the major architectural components of the MCB core. Throughout this document, the mcb is described as provided to the user by the memory ip tools within the Core generator software or edk environment. These tools typically produce top-level"wrapper"files that incorporate the embedded block memory controller primitive and any necessary soft logic and port mapping required to deliver the complete solution. For example, in Figure 1-1, the physical interface of the MCB uses the capabilities of the general I/o block (IOB)to implement the external interface to the memory. General I/o clock network resources are also used
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