FPGA_Zynq UltraScale+ MPSoC 数据手册：概述_（Xilinx）.pdf
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DS891 (v1.8) October 2, 2019 www.xilinx.com
Product Specification 1
© Copyright 2015–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are
trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, Arm1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, and MPCore are trademarks
of Arm in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and are used under license. All other trademarks are the property of their
respective owners.
General Description
The Zynq® UltraScale+™ MPSoC family is based on the Xilinx® UltraScale™ MPSoC architecture. This
family of products integrates a feature-rich 64-bit quad-core or dual-core Arm® Cortex™-A53 and
dual-core Arm Cortex-R5 based processing system (PS) and Xilinx programmable logic (PL) UltraScale
architecture in a single device. Also included are on-chip memory, multiport external memory interfaces,
and a rich set of peripheral connectivity interfaces.
Processing System (PS)
Arm Cortex-A53 Based Application
Processing Unit (APU)
• Quad-core or dual-core
• CPU frequency: Up to 1.5GHz
• Extendable cache coherency
• Armv8-A Architecture
o 64-bit or 32-bit operating modes
o TrustZone security
o A64 instruction set in 64-bit mode,
A32/T32 instruction set in 32-bit mode
• NEON Advanced SIMD media-processing engine
• Single/double precision Floating Point Unit (FPU)
• CoreSight™ and Embedded Trace Macrocell (ETM)
• Accelerator Coherency Port (ACP)
• AXI Coherency Extension (ACE)
• Power island gating for each processor core
• Timer and Interrupts
o Arm Generic timers support
o Two system level triple-timer counters
o One watchdog timer
o One global system timer
• Caches
o 32KB Level 1, 2-way set-associative
instruction cache with parity (independent for
each CPU)
o 32KB Level 1, 4-way set-associative data
cache with ECC (independent for each CPU)
o 1MB 16-way set-associative Level 2 cache
with ECC (shared between the CPUs)
Dual-core Arm Cortex-R5 Based
Real-Time Processing Unit (RPU)
• CPU frequency: Up to 600MHz
• Armv7-R Architecture
o A32/T32 instruction set
• Single/double precision Floating Point Unit (FPU)
• CoreSight™ and Embedded Trace Macrocell
(ETM)
• Lock-step or independent operation
• Timer and Interrupts:
o One watchdog timer
o Two triple-timer counters
• Caches and Tightly Coupled Memories (TCMs)
o 32KB Level 1, 4-way set-associative
instruction and data cache with ECC
(independent for each CPU)
o 128KB TCM with ECC (independent for each
CPU) that can be combined to become 256KB
in lockstep mode
On-Chip Memory
• 256KB on-chip RAM (OCM) in PS with ECC
• Up to 36Mb on-chip RAM (UltraRAM) with ECC in
PL
• Up to 35Mb on-chip RAM (block RAM) with ECC
in PL
• Up to 11Mb on-chip RAM (distributed RAM) in PL
Zynq UltraScale+ MPSoC Data Sheet:
Overview
DS891 (v1.8) October 2, 2019
Product Specification
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