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Preliminary Information
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Quartus II Version 7.2 Handbook
Volume 4: SOPC Builder
QII5V4-7.2
Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services.
ii Altera Corporation
Altera Corporation iii
Quartus II Handbook, Volume 4
Contents
Chapter Revision Dates ............................................................................ xi
About this Handbook.............................................................................. xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Section I. SOPC Builder Features
Chapter 1. Introduction to SOPC Builder
Overview ................................................................................................................................................. 1–1
Architecture of SOPC Builder Systems .............................................................................................. 1–2
SOPC Builder Components ............................................................................................................ 1–2
Example System .......................................................................................................................... 1–3
Custom Components .................................................................................................................. 1–4
System Interconnect Fabric ............................................................................................................. 1–5
Functions of SOPC Builder ................................................................................................................... 1–5
Defining and Generating the System Hardware ......................................................................... 1–5
Creating a Memory Map for Software Development ................................................................. 1–6
Creating a Simulation Model and Test Bench .............................................................................. 1–6
Getting Started ....................................................................................................................................... 1–7
Referenced Documents ......................................................................................................................... 1–7
Document Revision History ................................................................................................................. 1–8
Chapter 2. System Interconnect Fabric for Memory-Mapped Interfaces
Introduction ............................................................................................................................................ 2–1
High-Level Description ................................................................................................................... 2–1
Fundamentals of Implementation ................................................................................................. 2–4
Functions of System Interconnect Fabric ...................................................................................... 2–4
Address Decoding ................................................................................................................................. 2–5
Datapath Multiplexing .......................................................................................................................... 2–6
Wait-State Insertion ............................................................................................................................... 2–7
Pipeline Read Transfers ........................................................................................................................ 2–8
Native Address Alignment and Dynamic Bus Sizing ...................................................................... 2–9
Dynamic Bus Sizing ......................................................................................................................... 2–9
Wider Master ............................................................................................................................. 2–10
Narrower Master ....................................................................................................................... 2–10
Native Address Alignment ........................................................................................................... 2–11
Arbitration for Multimaster Systems ................................................................................................ 2–12
iv Altera Corporation
Quartus II Handbook, Volume 4
Quartus II Handbook, Volume 4
Traditional Shared Bus Architectures ......................................................................................... 2–12
Slave-Side Arbitration ................................................................................................................... 2–13
Arbiter Details ................................................................................................................................. 2–14
Arbitration Rules ............................................................................................................................ 2–15
Setting Arbitration Parameters in SOPC Builder ................................................................. 2–15
Fairness-Based Shares .............................................................................................................. 2–16
Round-Robin Scheduling ......................................................................................................... 2–17
Burst Transfers .......................................................................................................................... 2–17
Minimum Share Value ............................................................................................................. 2–17
Burst Management .............................................................................................................................. 2–18
Clock Domain Crossing ...................................................................................................................... 2–19
Description of Clock Domain-Crossing Logic ........................................................................... 2–19
Location of Clock Domain Crossing Logic ................................................................................. 2–21
Duration of Transfers Crossing Clock Domains ........................................................................ 2–22
Implementing Multiple Clock Domains in SOPC Builder ....................................................... 2–22
Component Overview ................................................................................................................... 2–23
Functional Description .................................................................................................................. 2–23
Interfaces .................................................................................................................................... 2–24
Clock Domain Crossing Logic and FIFOs ............................................................................. 2–24
Burst Support ............................................................................................................................. 2–25
Example System with Avalon-MM Clock-Crossing Bridges ............................................. 2–26
Instantiating the Avalon-MM Clock-Crossing Bridge in SOPC Builder ................................ 2–28
Interrupts .............................................................................................................................................. 2–29
Software Priority ............................................................................................................................ 2–29
Hardware Priority .......................................................................................................................... 2–30
Assigning IRQs in SOPC Builder ................................................................................................. 2–30
Reset Distribution ................................................................................................................................ 2–31
Referenced Documents ....................................................................................................................... 2–31
Document Revision History ............................................................................................................... 2–32
Chapter 3. System Interconnect Fabric for Streaming Interfaces
Introduction ............................................................................................................................................ 3–1
High-Level Description ................................................................................................................... 3–1
Avalon Streaming and Avalon Memory-Mapped Interfaces .................................................... 3–2
Adapters .................................................................................................................................................. 3–3
Data Format Adapter ....................................................................................................................... 3–4
Timing Adapter ................................................................................................................................ 3–4
Channel Adapter .............................................................................................................................. 3–5
Multiplexer Examples ........................................................................................................................... 3–5
Example to Double Clock Frequency ............................................................................................ 3–5
Example to Double Data Width and Maintain Frequency ......................................................... 3–6
Example to Boost the Frequency .................................................................................................... 3–6
Referenced Documents ......................................................................................................................... 3–7
Document Revision History ................................................................................................................. 3–7
Chapter 4. SOPC Builder Components
Introduction ............................................................................................................................................ 4–1
Altera Corporation v
Quartus II Handbook, Volume 4
Contents
New Component Structure in v7.1 of the Quartus II Software ................................................. 4–1
Component Providers ........................................................................................................................... 4–2
Component Hardware Structure ......................................................................................................... 4–2
Components That Include Logic Inside the System Module ..................................................... 4–3
Components That Interface to Logic Outside the System Module ........................................... 4–4
List of Available Components in SOPC Builder ............................................................................... 4–4
Tcl Components ..................................................................................................................................... 4–5
Component Description File (_hw.tcl) .......................................................................................... 4–5
Component File Organization ........................................................................................................ 4–5
Referenced Document ........................................................................................................................... 4–6
Document Revision History ................................................................................................................. 4–6
Chapter 5. Component Editor
Introduction ............................................................................................................................................ 5–1
Component Hardware Structure ......................................................................................................... 5–2
Starting the Component Editor ........................................................................................................... 5–2
HDL Files Tab ........................................................................................................................................ 5–2
Signals Tab .............................................................................................................................................. 5–3
Naming Signals for Automatic Type and Interface Recognition .............................................. 5–4
Templates for Interfaces to External Logic ................................................................................... 5–5
Interfaces Tab ......................................................................................................................................... 5–6
Component Wizard Tab ....................................................................................................................... 5–6
Identifying Information ................................................................................................................... 5–6
Parameters ......................................................................................................................................... 5–7
Saving a Component ............................................................................................................................. 5–7
Editing a Component ............................................................................................................................ 5–8
Referenced Documents ......................................................................................................................... 5–8
Document Revision History ................................................................................................................. 5–9
Chapter 6. Building a Component Interface with Tcl Scripting Commands
Organization of a Component Tcl File ............................................................................................... 6–2
Set and Add Commands ...................................................................................................................... 6–3
Module Properties ................................................................................................................................. 6–4
Clock Interface ....................................................................................................................................... 6–4
Avalon-MM Master Interface .............................................................................................................. 6–5
Avalon-MM Slave Interface ................................................................................................................. 6–5
Avalon-ST Source Interface .................................................................................................................. 6–6
Avalon-ST Sink Interface ...................................................................................................................... 6–7
Avalon-MM Tristate Interface ............................................................................................................. 6–7
Nios II Custom Instruction Interface .................................................................................................. 6–8
Interrupt Interface ................................................................................................................................. 6–9
Conduit Interface ................................................................................................................................. 6–10
Document Revision History ............................................................................................................... 6–10
Chapter 7. Archiving SOPC Builder Projects
Introduction ............................................................................................................................................ 7–1
Scope ........................................................................................................................................................ 7–1
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资源评论
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- 变硬金刚2013-05-08内容完整,可用
- cycjty2013-09-21其实也可以从官网下完整的5卷版,这个内容一致。
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