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Preliminary Information
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Quartus II Version 8.0 Handbook
Volume 4: SOPC Builder
QII5V4-8.0
Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services.
ii Altera Corporation
Altera Corporation iii
Quartus II Handbook, Volume 4
Contents
Chapter Revision Dates ............................................................................ xi
About this Handbook.............................................................................. xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Section I. SOPC Builder Features
Chapter 1. Introduction to SOPC Builder
Quick Start Guide .................................................................................................................................. 1–1
Overview ................................................................................................................................................. 1–1
Architecture of SOPC Builder Systems .............................................................................................. 1–2
SOPC Builder Modules .................................................................................................................... 1–2
Example System .......................................................................................................................... 1–3
Custom Components .................................................................................................................. 1–4
Functions of SOPC Builder ................................................................................................................... 1–5
Defining and Generating the System Hardware ......................................................................... 1–5
Creating a Memory Map for Software Development ................................................................. 1–6
Creating a Simulation Model and Test Bench .............................................................................. 1–6
Operating System Support ................................................................................................................... 1–6
Talkback Support ................................................................................................................................... 1–6
Referenced Documents ......................................................................................................................... 1–7
Document Revision History ................................................................................................................. 1–8
Chapter 2. System Interconnect Fabric for Memory-Mapped Interfaces
Introduction ............................................................................................................................................ 2–1
High-Level Description ................................................................................................................... 2–1
Fundamentals of Implementation ................................................................................................. 2–4
Functions of System Interconnect Fabric ...................................................................................... 2–4
Address Decoding ................................................................................................................................. 2–5
Datapath Multiplexing .......................................................................................................................... 2–6
Wait-State Insertion ............................................................................................................................... 2–7
Pipeline Read Transfers ........................................................................................................................ 2–7
Native Address Alignment and Dynamic Bus Sizing ...................................................................... 2–8
Dynamic Bus Sizing ......................................................................................................................... 2–9
Wider Master ............................................................................................................................. 2–10
Narrower Master ....................................................................................................................... 2–10
Arbitration for Multimaster Systems ................................................................................................ 2–11
iv Altera Corporation
Quartus II Handbook, Volume 4
Quartus II Handbook, Volume 4
Traditional Shared Bus Architectures ......................................................................................... 2–11
Slave-Side Arbitration ................................................................................................................... 2–12
Arbiter Details ................................................................................................................................. 2–13
Arbitration Rules ............................................................................................................................ 2–14
Setting Arbitration Parameters in SOPC Builder ................................................................. 2–15
Fairness-Based Shares .............................................................................................................. 2–15
Round-Robin Scheduling ......................................................................................................... 2–16
Burst Transfers .......................................................................................................................... 2–16
Minimum Share Value .............................................................................................................2–16
Burst Adapters ..................................................................................................................................... 2–17
Interrupts .............................................................................................................................................. 2–18
Individual Requests IRQ Scheme ................................................................................................ 2–18
Priority Encoded Interrupt Scheme ............................................................................................. 2–19
Assigning IRQs in SOPC Builder ................................................................................................. 2–19
Reset Distribution ................................................................................................................................ 2–20
Referenced Documents ....................................................................................................................... 2–20
Document Revision History ............................................................................................................... 2–21
Chapter 3. System Interconnect Fabric for Streaming Interfaces
Introduction ............................................................................................................................................ 3–1
High-Level Description ................................................................................................................... 3–1
Avalon Streaming and Avalon Memory-Mapped Interfaces .................................................... 3–2
Adapters .................................................................................................................................................. 3–3
Data Format Adapter ....................................................................................................................... 3–4
Timing Adapter ................................................................................................................................ 3–5
Channel Adapter .............................................................................................................................. 3–5
Multiplexer Examples ........................................................................................................................... 3–5
Example to Double Clock Frequency ............................................................................................ 3–5
Example to Double Data Width and Maintain Frequency ......................................................... 3–6
Example to Boost the Frequency .................................................................................................... 3–6
Referenced Documents ......................................................................................................................... 3–7
Document Revision History ................................................................................................................. 3–8
Chapter 4. SOPC Builder Components
Introduction ............................................................................................................................................ 4–1
Component Providers ........................................................................................................................... 4–1
Component Hardware Structure ......................................................................................................... 4–2
Components Inside the SOPC Builder System ............................................................................ 4–3
Components That Interface to Logic Outside the SOPC Builder System ................................ 4–4
Exported Connection Points ................................................................................................................ 4–4
Selecting Components in SOPC Builder ............................................................................................ 4–5
Component Structure ............................................................................................................................ 4–5
Component Description File (_hw.tcl) .......................................................................................... 4–6
Component File Organization ........................................................................................................ 4–6
Using Classic Components in SOPC Builder .................................................................................... 4–7
Referenced Document ........................................................................................................................... 4–7
Document Revision History ................................................................................................................. 4–8
Altera Corporation v
Quartus II Handbook, Volume 4
Contents
Chapter 5. Using SOPC Builder with the Quartus II Software
Introduction ............................................................................................................................................ 5–1
Quartus IP File ....................................................................................................................................... 5–1
Quartus II Incremental Compilation .................................................................................................. 5–2
TimeQuest Timing Analyzer ............................................................................................................... 5–2
Analyzing PLLs ................................................................................................................................ 5–3
Analyzing Slow Asynchronous I/O Paths ................................................................................... 5–5
Analyzing Single Data Rate SDRAM and SSRAM ...................................................................... 5–5
Analyzing Tri-state Bridge and Asynchronous Devices ............................................................ 5–8
Analyzing DDR and DDR2 Memories .......................................................................................... 5–9
Referenced Documents ....................................................................................................................... 5–10
Document Revision History ............................................................................................................... 5–10
Chapter 6. Component Editor
Introduction ............................................................................................................................................ 6–1
Component Hardware Structure ......................................................................................................... 6–2
Starting the Component Editor ........................................................................................................... 6–2
HDL Files Tab ........................................................................................................................................ 6–3
Signals Tab .............................................................................................................................................. 6–4
Naming Signals for Automatic Type and Interface Recognition .............................................. 6–4
Templates for Interfaces to External Logic ................................................................................... 6–6
Interfaces Tab ......................................................................................................................................... 6–6
Component Wizard Tab ....................................................................................................................... 6–6
Identifying Information ................................................................................................................... 6–6
Parameters ......................................................................................................................................... 6–7
Saving a Component ............................................................................................................................. 6–7
Editing a Component ............................................................................................................................ 6–8
Software Assignments .......................................................................................................................... 6–8
Component GUI ..................................................................................................................................... 6–8
Referenced Documents ......................................................................................................................... 6–8
Document Revision History ................................................................................................................. 6–9
Chapter 7. Component Interface Tcl Reference
Introduction ............................................................................................................................................ 7–1
Information in a Hardware Component Description File ............................................................... 7–1
Component Phases ................................................................................................................................ 7–2
Writing a Hardware Component Description File ........................................................................... 7–2
Providing Basic Information ........................................................................................................... 7–3
Declaring Parameters ....................................................................................................................... 7–3
Declaring Interfaces ......................................................................................................................... 7–4
Adding Files and Guiding Generation .......................................................................................... 7–4
Default Behaviors .................................................................................................................................. 7–5
Validation Phase Behavior .............................................................................................................. 7–5
Elaboration Phase Behavior ............................................................................................................ 7–6
Generation Phase Behavior ............................................................................................................. 7–6
Editor Phase Behavior ..................................................................................................................... 7–6
Overriding Default Behaviors .............................................................................................................. 7–6
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