iv Altera Corporation
Preliminary
Quartus II Handbook, Volume 1
Flat Compilation Flow with No Design Partitions ...................................................................... 2–3
Incremental Compilation Flow with Design Partitions .............................................................. 2–5
Top-Down versus Bottom-Up Compilation Flows ..................................................................... 2–9
Quick Start Guide – Summary of Steps for an Incremental Compilation Flow ......................... 2–11
Top-Down Incremental Compilation Flow ................................................................................ 2–11
Bottom-Up Incremental Compilation .......................................................................................... 2–13
Design Partitions .................................................................................................................................. 2–17
Design Partition Assignments Compared to Physical Placement Assignments .................. 2–18
Creating Design Partitions ................................................................................................................. 2–19
Partition Name ................................................................................................................................ 2–21
Setting the Netlist Type for Design Partitions ................................................................................. 2–22
Fitter Preservation Level ............................................................................................................... 2–24
Empty Partitions ............................................................................................................................. 2–26
What Represents a Source Change for Incremental Compilation? ......................................... 2–27
Creating a Design Floorplan With LogicLock Location Assignments ......................................... 2–29
Taking Advantage of the Early Timing Estimator .................................................................... 2–31
Exporting and Importing Partitions for Bottom-Up Design Flows .............................................. 2–32
Quartus II Exported Partition File (.qxp) .................................................................................... 2–32
Exporting a Lower-Level Partition to be Used in a Top-Level Project ................................... 2–33
Exporting a Lower-Level Block within a Project ....................................................................... 2–35
Importing a Lower-Level Partition Into the Top-Level Project ............................................... 2–36
Importing Assignments and Advanced Import Settings ......................................................... 2–37
Generating Bottom-Up Design Partition Scripts for Project Management ............................ 2–40
Guidelines for Creating Good Design Partitions and LogicLock Regions .................................. 2–46
Creating Good Design Partitions .................................................................................................2–47
Partition Statistics Reports ............................................................................................................ 2–50
Resource Balancing ........................................................................................................................ 2–51
Timing Budgeting .......................................................................................................................... 2–53
Methodology to Check Partition Quality during Partition Planning ..................................... 2–54
The Importance of Floorplan Location Assignments in Incremental Compilation .............. 2–55
Creating Good Floorplan Location Assignments ...................................................................... 2–57
Incremental Compilation Advisor ............................................................................................... 2–60
Criteria for Successful Partition and Floorplan Schemes ......................................................... 2–61
Recommended Design Flows and Compilation Application Examples ..................................... 2–62
Top-Down Incremental Design Flows ........................................................................................ 2–62
Bottom-Up Incremental Design Flows ........................................................................................ 2–67
Incremental Compilation Restrictions .............................................................................................. 2–76
Using Incremental Synthesis Only Instead of Full Incremental Compilation ...................... 2–76
Preserving Exact Timing Performance ........................................................................................ 2–77
Using Incremental Compilation with Quartus II Archive Files .............................................. 2–77
Formal Verification Support ......................................................................................................... 2–78
OpenCore Plus MegaCore Functions in Bottom-Up Flows ..................................................... 2–78
Importing Encrypted IP Cores in Bottom-Up Flows ................................................................ 2–78
SignalProbe Pins and Engineering Change Management with the Chip Planner ............... 2–78
SignalTap II Embedded Logic Analyzer in Bottom-Up Compilation Flows ......................... 2–80
Logic Analyzer Interface in Bottom-Up Compilation Flows ................................................... 2–81
Migrating Projects with Design Partitions to Different Devices ............................................. 2–81
