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TI-TUSB3410.pdf
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串口转USB
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB3410, TUSB3410I
SLLS519J –MARCH 2002–REVISED JULY 2017
TUSB3410 USB to Serial Port Controller
1 Device Overview
1
1.1 Features
1
• Fully Compliant With USB 2.0 Full-Speed
Specifications: TID#40340262
• Supports 12-Mbps USB Data Rate (Full Speed)
• Supports USB Suspend, Resume, and Remote
Wake-Up Operations
• Configurable to Bus-Powered and Self-Powered
Operation
• Supports a Total of Three Input and Three Output
(Interrupt, Bulk) Endpoints
• Integrated 8052 Microcontroller With:
– 256 × 8 RAM for Internal Data
– 10K × 8 ROM (With USB and I
2
C Bootloader)
– 16K × 8 RAM for Code Space Loadable From
Host or I
2
C Port
– 2K × 8 Shared RAM Used for Data Buffers and
Endpoint Descriptor Blocks (EDBs)
– Master I
2
C Controller for EEPROM Device
Access
– MCU Operates at 24 MHz, Providing 2-MIPS
Operation
– 128-ms Watchdog Timer
• Enhanced UART Features:
– Software and Hardware Flow Control
– Automatic RS-485 Bus Transceiver Control,
With and Without Echo
– Selectable IrDA Mode for Up to 115.2-kbps
Transfer
– Software-Selectable Baud Rate From 50 BPS to
921.6 kbps
– Programmable Serial-Interface Characteristics
– 5-, 6-, 7-, or 8-Bit Characters
– Even, Odd, or No Parity-bit Generation and
Detection
– 1-, 1.5-, or 2-Stop Bit Generation
– Line Break Generation and Detection
– Internal Test and Loopback Capabilities
– Modem Control Functions (CTS, RTS, DSR, RI
and DCD)
– Internal Diagnostic Capability
– Loopback Control for Communications
Link-Fault Isolation
– Break, Parity, Overrun, Framing-Error
Simulation
1.2 Applications
• Modems
• Peripherals:
Printers, Handheld Devices, and so on
• Medical Meters
• DSP and µC Interface
1.3 Description
The TUSB3410 device provides bridging between a USB port and an enhanced UART serial port. The
device contains an 8052 microcontroller unit (MCU) with 16KB of RAM that can be loaded from the host or
from the external onboard memory through an I
2
C. The device also contains 10KB of ROM that allows the
MCU to configure the USB port at boot time. The ROM code also contains an I
2
C bootloader. All device
functions (such as the USB command decoding, UART setup, and error reporting) are managed by the
internal MCU firmware in unison with the PC host.
Device Information
PART NUMBER PACKAGE BODY SIZE
TUSB3410
VQFN (32) 5.00 mm × 5.00 mm
LQFP (32) 7.00 mm × 7.00 mm
1. For all available packages, see the orderable addendum at the end of the data sheet.
12 MHz
Clock
Oscillator
DP
, DM
PLL and
Dividers
USB
TxR
24 MHz
10K 8×
ROM
8052
Core
8
8
8
16-Bit
Timers
16K 8×
RAM
8
2K × 8
SRAM
8 4
Port 3
8
P3.4
P3.3
P3.1
P3.0
USB
Serial
Interface
Engine
CPU-I/F
8
Suspend/
Resume
8
UBM
8
USB Buffer
Manager
8
8
SIN
I C
2
Controller
DMA-1
DMA-3
UART−1
SOUT
I
2
C Bus
RTS
CTS
DTR
DSR
TDM
Control
Logic
IR
Encoder
M
U
X
SOUT/IR_SOUT
IR
M
Decoder
SIN/IR_SIN
U
X
2 ×
Copyright © 2017, Texas Instruments Incorporated
2
TUSB3410, TUSB3410I
SLLS519J –MARCH 2002–REVISED JULY 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: TUSB3410
Device Overview Copyright © 2002–2017, Texas Instruments Incorporated
1.4 Functional Block Diagram
3
TUSB3410, TUSB3410I
www.ti.com
SLLS519J –MARCH 2002–REVISED JULY 2017
Submit Documentation Feedback
Product Folder Links: TUSB3410
Revision HistoryCopyright © 2002–2017, Texas Instruments Incorporated
Table of Contents
1 Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 1
1.3 Description............................................ 1
1.4 Functional Block Diagram ............................ 2
2 Revision History ......................................... 3
3 Pin Configuration and Functions..................... 4
3.1 Pin Diagrams ......................................... 4
4 Specifications ............................................ 6
4.1 Absolute Maximum Ratings .......................... 6
4.2 ESD Ratings.......................................... 6
4.3 Recommended Operating Conditions ................ 6
4.4 Thermal Information .................................. 6
4.5 Electrical Characteristics ............................. 7
4.6 Timing and Switching Characteristics Information.... 8
4.7 Typical Characteristics ............................... 9
5 Detailed Description .................................. 10
5.1 Overview ............................................ 10
5.2 Functional Block Diagram........................... 11
5.3 Device Functional Modes ........................... 11
5.4 Processor Subsystems.............................. 16
5.5 Memory.............................................. 24
5.6 Boot Modes.......................................... 67
6 Application, Implementation, and Layout ......... 84
6.1 Application Information.............................. 84
6.2 Typical Application .................................. 84
6.3 Layout ............................................... 88
6.4 Power Supply Recommendations .................. 90
6.5 Crystal Selection .................................... 90
6.6 External Circuit Required for Reliable Bus Powered
Suspend Operation ................................. 91
7 Device and Documentation Support ............... 92
7.1 Documentation Support ............................. 92
7.2 Related Links........................................ 92
7.3 Receiving Notification of Documentation Updates.. 92
7.4 Community Resources .............................. 92
7.5 Trademarks.......................................... 92
7.6 Electrostatic Discharge Caution..................... 92
7.7 Glossary............................................. 92
8 Mechanical Packaging and Orderable
Information .............................................. 93
8.1 Packaging Information .............................. 93
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (November 2015) to Revision J Page
• Changed pin 21 From: DTR To: active low DTR in the Pin Functions table.................................................. 5
• Changed the description of bit 7 CONT in USBCTL: USB Control Register (Addr:FFFCh), CONT= 0 From:
enabled To: disables, CONT= 1 From: disbaled To: enabled................................................................. 40
Changes from Revision H (April 2013) to Revision I Page
• Added Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section,
and Mechanical, Packaging, and Orderable Information section .............................................................. 1
• Deleted Ordering Information table. ................................................................................................ 1
4
TUSB3410, TUSB3410I
SLLS519J –MARCH 2002–REVISED JULY 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: TUSB3410
Pin Configuration and Functions Copyright © 2002–2017, Texas Instruments Incorporated
3 Pin Configuration and Functions
3.1 Pin Diagrams
RHB Package
32-Pin VQFN
Top View
VF Package
32-Pin LQFP
Bottom View
5
TUSB3410, TUSB3410I
www.ti.com
SLLS519J –MARCH 2002–REVISED JULY 2017
Submit Documentation Feedback
Product Folder Links: TUSB3410
Pin Configuration and FunctionsCopyright © 2002–2017, Texas Instruments Incorporated
(1) 3-state CMOS output (±4-mA drive and sink)
(2) TTL-compatible, hysteresis input
(3) 3-state CMOS output (±12-mA drive and sink)
(4) TTL-compatible, hysteresis input, with internal 100-µA active pullup resistor
(5) The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two
clock cycles and then the output is high impedance.
(6) 3-state CMOS output (±8-mA drive and sink)
(7) TTL-compatible input without hysteresis, with internal 100-µA active pullup resistor
(8) Normal or IR mode: 3-state CMOS output (±4-mA drive and sink)
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
CLKOUT 22 O
Clock output (controlled by bits 2 (CLKOUTEN) and 3(CLKSLCT) in the MODECNFG register (see
(1)
and
Section 5.5.5.5)
CTS 13 I UART: Clear to send
(2)
DCD 15 I UART: Data carrier detect
(2)
DM 7 I/O Upstream USB port differential data minus
DP 6 I/O Upstream USB port differential data plus
DSR 14 I UART: Data set ready
(2)
DTR 21 O UART: Data terminal ready
(1)
GND 8, 18, 28 GND Digital ground
P3.0 32 I/O General-purpose I/O 0 (port 3, terminal 0)
(3)(4)(5)
P3.1 31 I/O General-purpose I/O 1 (port 3, terminal 1)
(3)(4)(5)
P3.3 30 I/O General-purpose I/O 3 (port 3, terminal 3)
(3)(4)(5)
P3.4 29 I/O General-purpose I/O 4 (port 3, terminal 4)
(3)(4)(5)
PUR 5 O Pullup resistor connection
(6)
RESET 9 I Device master reset input
(2)
RI/CP 16 I UART: Ring indicator
(2)
RTS 20 O UART: Request to send
(1)
SCL 11 O
Master I
2
C controller: clock signal
(1)
SDA 10 I/O
Master I
2
C controller: data signal
(1)(4)
SIN/IR_SIN 17 I UART: Serial input data / IR Serial data input
(7)
SOUT/IR_SOUT 19 O UART: Serial output data / IR Serial data output
(8)
SUSPEND 2 O Suspend indicator terminal
(3)
. When this terminal is asserted high, the device is in suspend mode.
TEST0 23 I Test input (for factory test only). This terminal must be tied to VCC through a 10-kΩ resistor.
TEST1 24 I Test input (for factory test only)
(4)
. This terminal must be tied to VCC through a 10-kΩ resistor.
VCC 3, 25 PWR 3.3 V
VDD18 4 PWR
1.8-V supply. An internal voltage regulator generates this supply voltage when terminal VREGEN is low. When
VREGEN is high, 1.8 V must be supplied externally.
VREGEN 1 I This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator.
WAKEUP 12 I Remote wake-up request terminal. When low, wakes up system
(4)
X1/CLKI 27 I 12-MHz crystal input or clock input
X2 26 O 12-MHz crystal output
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