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SCL
SCL
SDA
P82B96
Main Enclosure Remote-Control Enclosure
3.3–5 V
3.3–5 V
12 V
12 V
12 V
Long Cables
3.3–5 V
3.3–5 V
SDA
P82B96
Product
Folder
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P82B96
SCPS144C –MAY 2006–REVISED MAY 2015
P82B96 I
2
C Compatible Dual Bidirectional Bus Buffer
1 Features 3 Description
The P82B96 device is a bus buffer that supports
1
• Operating Power-Supply Voltage Range
bidirectional data transfer between an I
2
C bus and a
of 2 V to 15 V
range of other bus configurations with different
• Can Interface Between I
2
C Buses Operating at
voltage and current levels.
Different Logic Levels (2 V to 15 V)
One of the advantages of the P82B96 is that it
• Longer Cables by allowing bus capacitance of
supports longer cables/traces and allows for more
400 pF on Main Side (Sx/Sy) and 4000 pF on
devices per I
2
C bus because it can isolate bus
Transmission Side (Tx/Ty)
capacitance such that the total loading (devices and
• Outputs on the Transmission Side (Tx/Ty) Have
trace lengths) of the new bus or remote I
2
C nodes
are not apparent to other I
2
C buses (or nodes). The
High Current Sink Capability for Driving Low-
restrictions on the number of I
2
C devices in a system
Impedance or High-Capacitive Buses
due to capacitance, or the physical separation
• Interface With Optoelectrical Isolators and Similar
between them, are greatly improved.
Devices That Need Unidirectional Input and
The device is able to provide galvanic isolation
Output Signal Paths by Splitting I
2
C Bus Signals
(optocoupling) or use balanced transmission lines
Into Pairs of Forward (Tx/Ty) and Reverse (Rx/Ry)
(twisted pairs), because separate directional Tx and
Signals
Rx signals are provided. The Tx and Rx signals may
• 400-kHz Fast I
2
C Bus Operation Over at Least
be connected directly (without causing bus latching),
20 Meters of Wire
to provide an bidirectional signal line with I
2
C
• Latch-Up Performance Exceeds 100 mA Per
properties (open-drain driver). Likewise, the Ty and
Ry signals may also be connected together to provide
JESD 78, Class II
an bidirectional signal line with I
2
C properties (open-
• ESD Protection Exceeds JESD 22
drain driver). This allows for a simple communication
design, saving design time and costs.
2 Applications
• HDMI DDC
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• Long I
2
C Communication
SOIC (8) 4.90 mm × 3.91 mm
• Galvanic I
2
C Isolation
VSSOP (8) 3.00 mm × 3.00 mm
• Industrial Communications
P82B96
PDIP (8) 9.81 mm × 6.35 mm
TSSOP (8) 3.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Long-Distance I
2
C Communications
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
![](https://csdnimg.cn/release/download_crawler_static/87426321/bg2.jpg)
P82B96
SCPS144C –MAY 2006–REVISED MAY 2015
www.ti.com
Table of Contents
1 Features.................................................................. 1 9 Detailed Description............................................ 13
9.1 Overview ................................................................. 13
2 Applications ........................................................... 1
9.2 Functional Block Diagram ....................................... 13
3 Description ............................................................. 1
9.3 Feature Description................................................. 14
4 Revision History..................................................... 2
9.4 Device Functional Modes........................................ 14
5 Description (continued)......................................... 3
10 Application and Implementation........................ 15
6 Pin Configuration and Functions......................... 4
10.1 Application Information.......................................... 15
7 Specifications......................................................... 5
10.2 Typical Applications .............................................. 17
7.1 Absolute Maximum Ratings ..................................... 5
11 Power Supply Recommendations ..................... 21
7.2 ESD Ratings.............................................................. 5
12 Layout................................................................... 21
7.3 Recommended Operating Conditions....................... 5
12.1 Layout Guidelines ................................................. 21
7.4 Thermal Information.................................................. 5
12.2 Layout Example .................................................... 21
7.5 Electrical Characteristics: V
CC
= 2.3 V to 2.7 V........ 6
13 Device and Documentation Support ................. 22
7.6 Electrical Characteristics: V
CC
= 3 V to 3.6 V........... 7
13.1 Community Resources.......................................... 22
7.7 Electrical Characteristics: V
CC
= 4.5 V to 5.5 V........ 8
13.2 Trademarks........................................................... 22
7.8 Electrical Characteristics: V
CC
= 15 V....................... 9
13.3 Electrostatic Discharge Caution............................ 22
7.9 Switching Characteristics........................................ 10
13.4 Glossary................................................................ 22
7.10 Typical Characteristics.......................................... 11
14 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information ................ 12
Information ........................................................... 22
4 Revision History
Changes from Revision B (July 2007) to Revision C Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Changed V
CC
pins to VCC pins in pinout diagrams................................................................................................................ 4
2 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
![](https://csdnimg.cn/release/download_crawler_static/87426321/bg3.jpg)
P82B96
www.ti.com
SCPS144C –MAY 2006–REVISED MAY 2015
5 Description (continued)
Two or more Sx or Sy I/Os must not be connected to each other on the same node. The P82B96 design does
not support this configuration. Bidirectional I
2
C signals do not have a direction control pin so, instead, slightly
different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A standard I
2
C low applied at
the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special
buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a standard
I
2
C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to
similar buffers that rely on special logic thresholds for their operation.
The Sx/Sy side of the P82B96 is intended for I
2
C logic voltage levels of I
2
C master and slave devices or Tx/Rx
signals of a second P82B96, if required. If Rx and Tx are connected, Sx can function as either the SDA or SCL
line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no
restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or
multi-point configuration (multiple P82B96 devices share the same Tx/Rx and Ty/Ry nodes) with the Tx/Rx and
Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.
In any design, the Sx pins of different devices should never be linked, because the resulting system would be
very susceptible to induced noise and would not support all I
2
C operating modes.
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: P82B96
![](https://csdnimg.cn/release/download_crawler_static/87426321/bg4.jpg)
1
2
3
4
5
6
7
8
Sx
Rx
Tx
GND
Ty
Ry
Sy
VCC
1
2
3
4
5
6
7
8
Ty
Ry
Sy
VCC
Sx
Rx
Tx
GND
1
2
3
4
5
6
7
8
Sx
Rx
Tx
GND
Ty
Ry
Sy
VCC
GND
1
2
3
4
5
6
7
8
Sx
Rx
Tx
Ty
Ry
Sy
VCC
P82B96
SCPS144C –MAY 2006 –REVISED MAY 2015
www.ti.com
6 Pin Configuration and Functions
P Package
D Package
8-Pin PDIP
8-Pin SOIC
(Top View)
(Top View)
DGK Package
8-Pin VSSOP
PW Package
(Top View)
8-Pin TSSOP
(Top View)
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 Sx I/O Serial data bus or SDA. Connect to V
CC
of I
2
C master through a pullup resistor.
2 Rx I Receive signal. Connect to V
CC
of P82B96 through a pullup resistor.
3 Tx O Transmit signal. Connect to V
CC
of P82B96 through a pullup resistor.
4 GND — Ground
5 Ty O Transmit signal. Connect to V
CC
of P82B96 through a pullup resistor.
6 Ry I Receive signal. Connect to V
CC
of P82B96 through a pullup resistor.
7 Sy I/O Serial clock bus or SCL. Connect to V
CC
of I
2
C master through a pullup resistor.
8 VCC I Supply voltage
4 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
![](https://csdnimg.cn/release/download_crawler_static/87426321/bg5.jpg)
P82B96
www.ti.com
SCPS144C –MAY 2006–REVISED MAY 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
V
CC
Supply voltage on VCC pin –0.3 18 V
Sx or Sy (SDA or SCL) –0.3 18
V
I
Voltage on buffered input V
Rx or Ry –0.3 18
Sx or Sy (SDA or SCL) –0.3 18
V
O
Voltage on buffered output V
Tx or Ty –0.3 18
Sx or Sy 250
I
O
Continuous output current mA
Tx or Ty 250
I
CC
Continuous current through VCC or GND 250 mA
T
A
Operating free-air temperature –40 85 °C
T
stg
Storage temperature –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE UNIT
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±3500
Charged-Device Model (CDM), per JEDEC specification JESD22- ±1000
V
(ESD)
Electrostatic discharge V
C101
(2)
Machine Model (MM), per JEDEC specification JESD22-A115-A ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN MAX UNIT
V
CC
Supply voltage 2 15 V
Sx, Sy V
Sx
, V
Sy
= 1 V, V
Rx
, V
Ry
≤ 0.42 V 3
I
OL
Low-level output current mA
Tx, Ty V
Sx
, V
Sy
= 0.4 V, V
Tx
, V
Ty
= 0.4 V 30
Sx, Sy V
Tx
, V
Ty
= 0.4 V 15
V
IOmax
Maximum input/output voltage level V
Tx, Ty V
Sx
, V
Sy
= 0.4 V 15
V
ILdiff
Low-level input voltage difference Sx, Sy 0.4 V
T
A
Operating free-air temperature –40 85 °C
7.4 Thermal Information
P82B96
THERMAL METRIC
(1)
D (SOIC) DGK (VSSOP) P (PDIP) PW (TSSOP) UNIT
8 PINS 8 PINS 8 PINS 8 PINS
R
θJA
Junction-to-ambient thermal resistance 109.1 174.3 53.5 173.5 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 61.6 63 44.4 57.6 °C/W
R
θJB
Junction-to-board thermal resistance 48.6 94.2 30.6 101.8 °C/W
ψ
JT
Junction-to-top characterization parameter 19.6 8.1 22.9 5.3 °C/W
ψ
JB
Junction-to-board characterization parameter 48.2 92.8 30.5 100.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: P82B96
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