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TSER953 4.16-Gbps V
3
Link Serializer With MIPI CSI-2 Interface for High-Speed, High-
Resolution Cameras, RADAR, and Other Sensors
1 Features
• 4.16-Gbps grade serializer supports high-speed
sensors including full HD 1080p 2.3MP 60-fps and
4MP 30-fps imagers
• Low (0.25 W typical) power consumption
• IEC 61000-4-2 ESD compliant
• Power-over-Coax (PoC) compatible transceiver
• D-PHY v1.2 and CSI-2 v1.3 compliant system
interface
– Up to 4 data lanes at 832 Mbps per each lane
– Supports up to four virtual channels
• Precision multi-camera clocking and
synchronization
• Flexible programmable output clock generator
• Advanced data protection and diagnostics
including CRC data protection, sensor data
integrity check, I2C write protection, voltage and
temperature measurement, programmable alarm,
and line fault detection
• Supports Single-ended coaxial or shielded-twisted-
pair (STP) cable
• Ultra-low latency bidirectional I
2
C and GPIO
control channel enables ISP control from ECU
• Single 1.8-V power supply
• Compatible with TDES954 and TDES960
deserializers
• Wide temperature range: –20°C to 85°C
• Small 5-mm × 5-mm VQFN package and PoC
solution size for compact camera module designs
2 Applications
• Appliances
• Video surveillance
• Elevators and escalators
• Industrial robots
• Machine vision
• Patient monitoring and diagnostics
• Imaging
3 Description
The TSER953 serializer is part of TI's V
3
Link device
family designed to support high-speed raw data
sensors including 2.3MP imagers at 60-fps and
as well as 4MP, 30-fps cameras, satellite RADAR,
LIDAR, and Time-of-Flight (ToF) sensors. The device
delivers a 4.16-Gbps forward channel and an ultra-
low latency, 50-Mbps bidirectional control channel
and supports power over a single coax (PoC) or
STP cable. The TSER953 features advanced data
protection and diagnostic features to support high-
speed data transmission for various applications, such
as robotics and automation, medical imaging, and
security or surveillance, while streamlining design in
industrial and medical camera applications. Together
with a companion deserializer, the TSER953 delivers
precise multi-camera sensor clock and sensor
synchronization.
The serializer comes in a small 5-mm × 5-mm VQFN
package for space-constrained sensor applications.
Device Information
PART NUMBER PACKAGE
(1)
BODY SIZE (NOM)
TSER953 VQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Image
Signal
Processor
(ISP)
Full HD
Image Sensor
V
3
Link
(over Coax or STP)
TSER953
Serializer
TDES954
or
TDES960
Deserializer
DOUT+/-
RIN+/-
MIPI CSI-2
D3P/N
CLKP/N
D2P/N
D1P/N
D0P/N
I2C
HS-GPIO
MIPI CSI-2
D3P/N
CLKP/N
D2P/N
D1P/N
D0P/N
I2C
HS-GPIO
Typical Application
TSER953
SNLS696A – APRIL 2021 – REVISED MAY 2021
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................8
6.6 Recommended Timing for the Serial Control Bus..... 11
6.7 Timing Diagrams.......................................................12
6.8 Typical Characteristics.............................................. 12
7 Detailed Description......................................................13
7.1 Overview................................................................... 13
7.2 Functional Block Diagram......................................... 13
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................20
7.5 Programming............................................................ 24
7.6 Pattern Generation....................................................26
7.7 Register Maps...........................................................30
8 Application and Implementation.................................. 64
8.1 Application Information............................................. 64
8.2 Typical Applications.................................................. 67
9 Power Supply Recommendations................................71
9.1 Power-Up Sequencing.............................................. 71
9.2 Power Down (PDB)...................................................72
10 Layout...........................................................................73
10.1 Layout Guidelines................................................... 73
10.2 Layout Examples.................................................... 74
11 Device and Documentation Support..........................76
11.1 Documentation Support.......................................... 76
11.2 Receiving Notification of Documentation Updates.. 76
11.3 Support Resources................................................. 76
11.4 Trademarks............................................................. 76
11.5 Electrostatic Discharge Caution.............................. 76
11.6 Glossary.................................................................. 76
12 Mechanical, Packaging, and Orderable
Information.................................................................... 77
4 Revision History
Changes from Revision * (April 2021) to Revision A (May 2021) Page
• Updated images with searchable text and layout............................................................................................... 1
TSER953
SNLS696A – APRIL 2021 – REVISED MAY 2021
www.ti.com
2 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TSER953
5 Pin Configuration and Functions
TSER953
32L QFN
(Top View)
32
31
30
29
28
27
26
25
CSI_D2P
CSI_D3N
CSI_D3P
GPIO_3
GPIO_2
VDDD_CAP
VDDD
DAP = GND
CSI_D2N
9
10
11
12
13
14
15
16
LPF1
VDDDRV
VDDPLL_CAP
VDDPLL
LPF2
DOUT-
VDDDRV_CAP
DOUT+
24
23
22
21
20
19
18
17
GPIO_1
CLK_OUT/IDX
RES1
I2C_SDA
GPIO_0
MODE
I2C_SCL
CLKIN
1
2
3
4
5
6
7
8
RES0
CSI_CLKN
CSI_D0P
CSI_D1N
CSI_D1P
CSI_D0N
CSI_CLKP
PDB
Figure 5-1. RHB Package
32-Pin VQFN
Top View
www.ti.com
TSER953
SNLS696A – APRIL 2021 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TSER953
Table 5-1. Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
CSI INTERFACE
CSI_CLKP 5 I, DPHY
CSI-2 clock input pins. Connect to a CSI-2 clock source with matched 100-Ω (±5%)
impedance interconnects.
CSI_CLKN 6 I, DPHY
CSI_D0P 3 I, DPHY
CSI-2 data input pins. Connect to a CSI-2 data sources with matched 100-Ω (±5%)
impedance interconnects. If unused, these pins may be left floating.
CSI_D0N 4 I, DPHY
CSI_D1P 1 I, DPHY
CSI_D1N 2 I, DPHY
CSI_D2P 31 I, DPHY
CSI_D2N 32 I, DPHY
CSI_D3P 29 I, DPHY
CSI_D3N 30 I, DPHY
SERIAL CONTROL INTERFACE
I2C_SDA 23 OD I2C Data and Clock Pins. Typically pulled up by 470-Ω to 4.7-kΩ resistors to either 1.8-V or
3.3-V supply rail depending on IDX setting. See I2C Interface Configuration for further details
on the I2C implementation of the device. Documentation is also available to aid with I2C
pullup resistor calculation (SLVA689).
I2C_SCL 24 OD
CONFIGURATION and CONTROL
RES0 7 I Reserved pin – Connect to GND
RES1 22 I Reserved pin – Do not connect (leave floating)
PDB 8 I, PD
Power-down inverted Input Pin. Internal 1-MΩ pulldown. Typically connected to processor
GPIO with pull down. When PDB input is brought HIGH, the device is enabled and internal
register and state machines are reset to default values. Asserting PDB signal low will power
down the device and consume minimum power. The default function of this pin is PDB =
LOW; POWER DOWN. PDB should remain low until after power supplies are applied and
reach minimum required levels. See Power Down (PDB) for further details on the function of
PDB.
PDB INPUT IS NOT 3.3-V TOLERANT.
PDB = 1.8 V, device is enabled (normal operation)
PDB = 0, device is powered down.
MODE
21 I, S
Mode select configuration input. Default operational mode will be strapped at start-up based
on the MODE input voltage when PDB transitions LOW to HIGH. Typically connected
to voltage divider through external pullup to VDD18 and pulldown to GND applying an
appropriate bias voltage. See MODE for details.
CLK_OUT/IDX 19 I/O, S
IDX pin sets the I2C pullup voltage and device address; connect to external pullup to VDD
and pulldown to GND to create a voltage divider. When PDB transitions LOW to HIGH, the
strap input voltage is sensed at the CLOCK_OUT/IDX pin to determine functionality and then
converted to CLK_OUT. See I2C Interface Configuration for details. If CLK_OUT is used, the
minimum resistance on the pin is 35 kΩ. If unused, CLK_OUT/IDX may be tied to GND.
V
3
LINK INTERFACE
DOUT- 13 I/O
V
3
Link Input/Output pins. These pins must be AC-coupled. See Figure 8-5 and Figure 8-6 for
typical connection diagrams and Table 8-3 for recommended capacitor values.
DOUT+ 14 I/O
POWER AND GROUND
VDDD_CAP 26 D, P
A connection for an internal analog regulator decoupling capacitor. Typically connected to
10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See
Typical Application for more details.
VDDDRV_CAP 15 D, P
A connection for an internal analog regulator decoupling capacitor. Typically connected to
10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See
Typical Application for more details.
VDDPLL_CAP 10 D, P
A connection for an internal analog regulator decoupling capacitor. Typically connected to
10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See
Typical Application for more details.
TSER953
SNLS696A – APRIL 2021 – REVISED MAY 2021
www.ti.com
4 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TSER953
Table 5-1. Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
VDDD 25 P
1.8-V (±5%) Power Supply pin.
Typically connected to 1-µF and 0.01-µF capacitors to GND.
VDDDRV 16 P
1.8-V (±5%) Analog Power Supply pin.
Typically connected to 1-µF and 0.01-µF capacitors to GND.
VDDPLL 11 P
1.8-V (±5%) Analog Power Supply pin.
Typically connected to 1-µF and 0.01-µF capacitors to GND.
GND DAP G
DAP is the large metal contact at the bottom side, located at the center of the VQFN
package. Connect to the ground plane (GND).
LOOP FILTER
LPF1 9 P Loop Filter 1: Connect as described in Section 8.2.2.4.
LPF2 12 P Loop Filter 2: Connect as described in Section 8.2.2.4.
CLOCK INTERFACE AND GPIO
GPIO_0 17 I/O, PD General-Purpose Input/Output pins. These pins can also be configured to sense the voltage
at their inputs. See Voltage and Temperature Sensing. At power up, these GPIO pins default
to inputs with a 300-kΩ (typical) internal pulldown resistor. These pins may be left floating
if unused, but TI recommends to set the GPIOx_INPUT_EN to 0 to disable the pins. See
Section 7.3.6 for programmability.
GPIO_1 18 I/O, PD
GPIO_2 27 I/O, PD General-Purpose Input/Output pins. At power up, these GPIO pins default to inputs with a
300-kΩ (typical) internal pulldown resistor. These pins may be left floating if unused, but TI
recommends to set the GPIOx_INPUT_EN to 0 to disable the pins. See Section 7.3.6 for
programmability.
GPIO_3 28 I/O, PD
CLKIN 20 I
Reference Clock Input pin. If operating in non-sync external clock mode, connect this pin to
a local clock source. If unused (like other clocking modes), this pin may be left open. See
Table 7-6 for more information on clocking modes.
www.ti.com
TSER953
SNLS696A – APRIL 2021 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TSER953
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