TI-DP83TC811R-Q1.pdf资源-CSDN文库

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TI-DP83TC811R-Q1是一款专为汽车工业设计的100Mbps以太网PHY收发器，适用于汽车以太网物理层的通信。该器件符合IEEE 802.3bw标准，是针对汽车网络的100BASE-T1规范，同时也符合OPEN Alliance的相关标准，确保了与其他BroadR-Reach和100BASE-T1 PHY设备的互操作性。 DP83TC811R-Q1满足AEC-Q100标准，适用于汽车的恶劣环境，其工作温度范围为-40°C至+125°C，拥有高ESD保护级别，确保了在汽车环境中的可靠性和耐用性。器件提供了多种MAC接口，包括MII（媒体独立接口）、RMII（减小的媒体独立接口）和RGMII（减小的吉比特媒体独立接口），以适应不同的网络连接需求。此器件采用VQFN封装，支持IEEE 1588 SFD（同步光纤网络快速帧差分），这是一种用于精确时间协议，有助于实现网络设备间的时间同步。DP83TC811R-Q1还具备低发送和接收延迟，符合AVB/TSN（音频视频桥接/时间敏感网络）标准，适合需要实时通信的应用场景。在节能方面，该PHY收发器提供了睡眠、待机和禁用等模式，支持局域网唤醒（WoL）功能，降低功耗。此外，DP83TC811R-Q1配备了一套全面的诊断工具，包括信号质量指标（SQI）、时域反射法（TDR）用于检查电缆质量，以及静电放电传感器、电压传感器、温度传感器和PRBS内置自检功能，这些工具能帮助检测和优化网络性能。在应用上，DP83TC811R-Q1广泛适用于汽车网络的核心主干、网关、车身控制系统以及远程信息处理。其36引脚的6.00mm x 6.00mm VQFN封装设计使得在有限的空间内也能实现高效能的网络连接。总体来说，TI-DP83TC811R-Q1是一款高性能、低功耗、功能丰富的汽车以太网PHY收发器，旨在为汽车行业的网络连接提供稳定、安全和高效的解决方案。其丰富的诊断工具和兼容性特性，使得该器件成为汽车电子系统中不可或缺的一部分。

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CPU/MPU

MAC

DP83TC811R-Q1

100 Mbps

Automotive Ethernet PHY

25-MHz

Clock Source

Status

LEDs

MII

RMII

RGMII

100BASE-T1

IEEE 802.3bw

Automotive

Connector

GND

CMC

Termination

Product

Folder

Order

Now

Technical

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Tools &

Software

Support &

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Reference

Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS551

DP83TC811R-Q1

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

DP83TC811R-Q1 低低功功耗耗汽汽车车 PHY

100BASE-T1 汽汽车车以以太太网网物物理理层层收收发发器器

1 特特性性

• 符合 100BASE-T1 – IEEE 802.3bw 标准

– 符合 OPEN Alliance 标准

– 能够与 BroadR-Reach和 100BASE-T1 PHY 进

行互操作

• 符合面向汽车应用的 AEC-Q100 标准：

– 器件温度等级 1：环境工作温度范围为 –40°C

至 +125°C

– 器件 HBM ESD 分类等级 3A

– 除引脚 5 之外，其他所有引脚的器件 CDM

ESD 分类等级均为 C5

– 引脚 5 的器件 CDM ESD 分类等级为 C3

– 引脚 12 和 13 的器件 IEC61000-4-2 ESD 分类

等级为 4：±8kV 接触放电

• MAC 接口：MII、RMII 和 RGMII

• VQFN，可湿侧面封装

• 支持 IEEE 1588 SFD

• 符合 AVB/TSN 标准的低发送和接收延迟

• 低有功功率运行：< 230mW

• 可配置的 I/O 电压：3.3V、2.5V 和 1.8V

• 节能特性：

– 睡眠、待机和禁用

– 局域网唤醒 (WoL)

• 诊断工具套件

– 信号质量指标 (SQI)

– 时域反射法 (TDR)

– 静电放电传感器

– 电压传感器

– 温度传感器

– PRBS 内置自检

2 应应用用

• 主干网络

• 网关和车身控制

• 远程信息处理

3 说说明明

DP83TC811R-Q1 器件是一款符合 IEEE 802.3bw 标

准的汽车 PHYTER™以太网物理层收发器。它提供通

过单一屏蔽双绞线电缆发送和接收数据所需的所有物理

层功能。该器件具有 xMII 灵活性，支持标准 MII、

RMII 和 RGMII MAC 接口。

该器件包含诊断工具套件，从而提供广泛的实时监控工

具、调试工具和测试模式。该工具套件中包含首款集成

式静电放电 (ESD) 监控工具。它能够对 xMII 和 MDI

上的 ESD 事件进行计数，并且能够通过使用可编程中

断提供实时监控。此外，DP83TC811R-Q1 还包含一

个假随机二进制序列 (PRBS) 帧生成工具，该工具与内

部回送完全兼容，能够在不使用 MAC 的情况下发送和

接收数据。DP83TC811R-Q1 采用 6.00mm ×

6.00mm、36 引脚 VQFN 可湿侧面封装。

器器件件信信息息

(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

DP83TC811R-Q1 VQFN (36) 6.00mm x 6.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

空白

简简化化原原理理图图

DP83TC811R-Q1

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Device Comparison Table..................................... 3

6 Pin Configuration and Functions......................... 3

6.1 Pin Multiplexing......................................................... 8

7 Specifications......................................................... 9

7.1 Absolute Maximum Ratings ...................................... 9

7.2 ESD Ratings.............................................................. 9

7.3 Recommended Operating Conditions....................... 9

7.4 Thermal Information.................................................. 9

7.5 Electrical Characteristics......................................... 10

7.6 Timing Requirements.............................................. 11

7.7 Timing Diagrams..................................................... 14

7.8 Typical Characteristics............................................ 20

8 Detailed Description............................................ 21

8.1 Overview ................................................................. 21

8.2 Functional Block Diagram ....................................... 22

8.3 Feature Description................................................. 23

8.4 Device Functional Modes........................................ 30

8.5 Programming........................................................... 42

8.6 Register Maps......................................................... 46

9 Application and Implementation ...................... 111

9.1 Application Information.......................................... 111

9.2 Typical Applications .............................................. 111

10 Power Supply Recommendations ................... 117

11 Layout................................................................. 117

11.1 Layout Guidelines ............................................... 117

11.2 Layout Example .................................................. 120

12 器器件件和和文文档档支支持持 ................................................... 122

12.1 接收文档更新通知 ............................................... 122

12.2 社区资源.............................................................. 122

12.3 商标 ..................................................................... 122

12.4 静电放电警告....................................................... 122

12.5 Glossary.............................................................. 122

13 机机械械、、封封装装和和可可订订购购信信息息..................................... 122

4 修修订订历历史史记记录录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (November 2017) to Revision A Page

• 将器件状态从“预告信息”更改成了“生产数据” ......................................................................................................................... 1

DP83TC811R-Q1

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

www.ti.com.cn

(1) When pins are unused, follow the recommended connection requirements provided in the table above. If pins do not have required

termination, they may be left floating.

(2) Pin Type:

I = Input

O = Output

IO = Input/Output

OD = Open Drain

PD = Internal pulldown

PU = Internal pullup

S = Bootstrap configuration pin (all configuration pins have weak internal pullups or pulldowns)

Pin Functions

(1)

STATE

(2)

DESCRIPTION

NAME NO.

MAC INTERFACE

RX_D3

S, PD, O

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins

synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A data

nibble, RX_D[3:0], is transmitted in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII

mode. RX_D[3:2] are not used when in RMII mode.

If the PHY is bootstrapped to RMII Master mode, a 50-MHz clock reference is automatically outputted

on RX_D3. This clock should be fed to the MAC.

RX_D2

RX_D1

RX_D0

RX_CLK 27 O

Receive Clock: In MII and RGMII modes, the receive clock provides a 25-MHz reference clock.

Unused in RMII mode

RX_ER 14 S, PD, O

Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected

within a received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of

RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference

clock. This pin is not required to be used by the MAC in MII or RMII because the PHY will

automatically corrupt data on a receive error.

Unused in RGMII mode

RX_DV

CRS_DV

RX_CTRL

15 S, PD, O

Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode.

Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous

signal. When CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode.

RGMII Receive Control: Receive control combines receive data valid indication and receive error

indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is

presented on the falling edge of RX_CLK.

TX_CLK 28 PD, I, O

Transmit Clock: In MII mode, the transmit clock is a 25-MHz output and has constant phase

referenced to the reference clock. In RGMII mode, this clock is sourced from the MAC layer to the

PHY. A 25-MHz clock should be provided (not required to have constant phase to the reference clock

unless synchronous RGMII is enabled in ).

Unused in RMII mode

TX_EN

TX_CTRL

29 PD, I

Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit

clock. TX_EN indicates the presence of valid data inputs on TX_D[3:0]. In RMII mode, transmit

enable is presented prior to the rising edge of the reference clock. TX_EN indicates the presence of

valid data inputs on TX_D[1:0].

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication

into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented

prior to the falling edge of TX_CLK.

TX_D3 30

PD, I

Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the

MAC prior to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to

the rising edge of the reference clock. TX_D[3:2] are not used in RMII mode.

TX_D2 31

TX_D1

TX_D0

TX_ER 34 PD, I

Transmit Error: In MII mode, this pin indicates a transmit error symbol has been detected within a

transmitted packet. TX_ER is received prior to the rising edge of TX_CLK.

Unused in RMII and RGMII modes

DP83TC811R-Q1

www.ti.com.cn

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

Pin Functions

(1)

(continued)

STATE

(2)

DESCRIPTION

NAME NO.

SERIAL MANAGEMENT INTERFACE

MDC 1 I

Management Data Clock: Synchronous clock to the MDIO serial management input and output

data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock

rate is 25 MHz. There is no minimum clock rate.

MDIO 36 IO

Management Data Input/Output: Bidirectional management data signal that may be sourced by the

management station or the PHY. This pin requires a pullup resistor.

Recommended to use a resistor between 2.2 kΩ and 9 kΩ.

CONTROL INTERFACE

INT 2 PU, OD, O

Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This

pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers.

Once an interrupt event flag is set, register access is required to clear the interrupt event.

Note: Power-on-RESET (POR) Done interrupt is enabled by default. POR Done interrupt can be

cleared by reading register INT_STAT3 Register 0x0018 – Interrupt Status Register #3.

This pin can be configured as an Active-HIGH output using register INT_TEST Register 0x0011 –

Interrupt Test Register.

RESET 3 PU, I

Reset: Active-LOW input, which initializes or reinitializes the DP83TC811R-Q1. Asserting this pin

LOW for at least 1 μs will force a reset process to occur. All internal registers will reinitialize to their

default states as specified for each bit in the Register Maps section. All bootstrap pins are resampled

upon deassertion of reset.

EN 7 PD, I

Enable: Active-HIGH input, which will disable the DP83TC811R-Q1 when pulled LOW and power

down all internal blocks. Disable state is equivalent to a power-down state.

This pin can be directly tied to VDDIO; enabling the device.

WAKE 8 PD, I

WAKE: Active-HIGH input, which wakes the PHY from SLEEP. Asserting this pin HIGH at power-up

will prevent the PHY from going to SLEEP.

This pin can be directly tied to VDDIO to wake the device.

INH 10 O

INH: Active-HIGH output, which will be asserted HIGH when the PHY is in SLEEP or DISABLED.

This pin is LOW for all other PHY states.

CLOCK INTERFACE

XI 5 I

Reference Clock Input (MII and RGMII): Reference clock 25-MHz ±100 ppm-tolerance crystal or

oscillator input. The device supports either an external crystal resonator connected across pins XI

and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating.

Reference Clock Input (RMII): Reference clock 50-MHz ±100 ppm-tolerance CMOS-level oscillator

in RMII Slave mode. Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator in RMII Master

mode.

This is a fail-safe pin. When the PHY is not powered, an external oscillator is allowed to be powered

and driving into this pin. Fail-safe prevents pin back-driving.

XO 4 O

Reference Clock Output: XO pin is used for crystal only. This pin should be left floating when a

CMOS-level oscillator is connected to XI.

LED/GPIO INTERFACE

LED_0 /

GPIO_0

35 S, PD, IO

LED_0: Link Status

LED_1 /

GPIO_1

6 S, PD, IO

LED_1: Link Status and BLINK for TX/RX Activity

CLKOUT /

GPIO_2

16 IO

Clock Output: 25-MHz reference clock

MEDIUM DEPENDENT INTERFACE

TRD_M 13

Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1

operation, IEEE 802.3bw compliant.

TRD_P 12

JTAG (IEEE 1149.1)

TCK 17 PU, I

Test Clock: Primary clock source for all test logic input and output. This pin is controlled by the

testing entity.

This pin can be left unconnected if not used.

剩余129页未读，继续阅读

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