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DESCRIPTION/ORDERING INFORMATION
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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BIASV
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
2A1
2A2
V
CC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
SN74CBTLV16800
LOW-VOLTAGE 20-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS
SCDS045J – DECEMBER 1997 – REVISED MARCH 2005
• Member of the Texas Instruments Widebus™
Family
• 5- Ω Switch Connection Between Two Ports
• Rail-to-Rail Switching on Data I/O Ports
• I
off
Supports Partial-Power-Down Mode
Operation
• B-Port Outputs Are Precharged by Bias
Voltage to Minimize Signal Distortion During
Live Insertion
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
The SN74CBTLV16800 provides 20 bits of
high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay. The device
also precharges the B port to a user-selectable bias
voltage (BIASV) to minimize live-insertion noise.
The device is organized as dual 10-bit bus switches
with separate output-enable ( OE) inputs. It can be
used as two 10-bit bus switches or one 20-bit bus
switch. When OE is low, the associated 10-bit bus
switch is on, and port A is connected to port B. When
OE is high, the switch is open, the high-impedance
state exists between the two ports, and port B is
precharged to BIASV through the equivalent of a
10-k Ω resistor.
<br/>
This device is fully specified for partial-power-down applications using I
off
. The I
off
feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SN74CBTLV16800DL
SSOP – DL CBTLV16800
Tape and reel SN74CBTLV16800DLR
–40 ° C to 85 ° C
TSSOP – DGG Tape and reel SN74CBTLV16800GR CBTLV16800
TVSOP – DGV Tape and reel SN74CBTLV16800VR CN800
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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