4
HD3SS214
ZHCSEP9B –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
Copyright © 2015–2017, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O DESCRIPTION
(1)
NO. NAME
A6 DA2(n) I/O Port A, Channel 2, High Speed Negative Signal
A8 DA3(p) I/O Port A, Channel 3, High Speed Positive Signal
A9 DA3(n) I/O Port A, Channel 3, High Speed Negative Signal
B1 DC0(n) I/O Port C, Channel 0, High Speed Negative Signal
B2 DC0(p) I/O Port C, Channel 0, High Speed Positive Signal
B3,C8,G2,G
8,H4,H7
GND Supply Ground
B4 DA0(p) I/O Port A, Channel 0, High Speed Positive Signal
B5 DA1(p) I/O Port A, Channel 1, High Speed Positive Signal
B6 DA2(p) I/O Port A, Channel 2, High Speed Positive Signal
B7 OE I
Output Enable:
OE = V
IH
: Normal Operation
OE = V
IL
: Standby Mode
B8 DB0(p) I/O Port B, Channel 0, High Speed Positive Signal
B9 DB0(n) I/O Port B, Channel 0, High Speed Negative Signal
C2 AUX_SEL Control I AUX/DDC Selection Control Pin in Conjunction with Dx_SEL Pin
D1 DC1(n) I/O Port C, Channel 1, High Speed Negative Signal
D2 DC1(p) I/O Port C, Channel 1, High Speed Positive Signal
D8 DB1(p) I/O Port B, Channel 1, High Speed Positive Signal
D9 DB1(n) I/O Port B, Channel 1, High Speed Negative Signal
E1 DC2(n) I/O Port C, Channel 2, High Speed Negative Signal
E2 DC2(p) I/O Port C, Channel 2, High Speed Positive Signal
E8 DB2(p) I/O Port B, Channel 2, High Speed Positive Signal
E9 DB2(n) I/O Port B, Channel 2, High Speed Negative Signal
F1 DC3(n) I/O Port C, Channel 3, High Speed Negative Signal
F2 DC3(p) I/O Port C, Channel 3, High Speed Positive Signal
F8 DB3(p) I/O Port B, Channel 3, High Speed Positive Signal
F9 DB3(n) I/O Port B, Channel 3, High Speed Negative Signal
H1 AUXC(n) I/O Port C AUX Negative Signal
H2 AUXC(p) I/O Port C AUX Positive Signal
H3 HPDB I/O Port B Hot Plug Detect
H6 AUXB(p) I/O Port B AUX Positive Signal
H5 DDCCLK_B I/O Port B DDC Clock Signal
H8 DDCCLK_A I/O Port A DDC Clock Signal
H9 AUXA(p) I/O Port A AUX Positive Signal
J1 HPDC I/O Port C Hot Plug Detect
J2 HPDA I/O Port A Hot Plug Detect
J3 DDCCLK_C I/O Port C DDC Clock Signal
J5 DDCDAT_B I/O Port B DDC Data Signal
J6 AUXB(n) I/O Port B AUX Negative Signal
J7 DDCDAT_C I/O Port C DDC Data Signal
J8 DDCDAT_A I/O Port A DDC Data Signal
J9 AUXA(n) I/O Port A AUX Negative Signal
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