没有合适的资源?快使用搜索试试~ 我知道了~
TI-THS1206M.pdf
需积分: 5 0 下载量 18 浏览量
2022-11-27
00:06:54
上传
评论 4
收藏 1.11MB PDF 举报
温馨提示
试读
43页
TI-THS1206M.pdf
资源推荐
资源详情
资源评论
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANA-
LOG-TO-DIGITAL CONVERTERS
FEATURES
D
High-Speed 6 MSPS ADC
D
4 Analog Inputs
D
Simultaneous Sampling of 4 Single-Ended
Signals or 2 Differential Signals or
Combination of Both
D
Differential Nonlinearity Error: ±1 LSB
D
Integral Nonlinearity Error: ±1.5 LSB
D
Signal-to-Noise and Distortion Ratio: 68 dB
at f
I
= 2 MHz
D
Auto-Scan Mode for 2, 3, or 4 Inputs
D
3-V or 5-V Digital Interface Compatible
D
Low Power: 216 mW Max
D
5-V Analog Single Supply Operation
D
Internal Voltage References ...50 PPM/°C
and ±5% Accuracy
D
Glueless DSP Interface
D
Parallel µC/DSP Interface
D
Integrated FIFO
D
Available in TSSOP Package
D
Pin Compatible Upgrade to THS10064
APPLICATIONS
D
Radar Applications
D
Communications
D
Control Applications
D
High-Speed DSP Front-End
D
Automotive Applications
DESCRIPTION
The THS1206 is a CMOS, low-power, 12-bit, 6 MSPS
analog-to-digital converter (ADC). The speed, resolution,
bandwidth, and single-supply operation are suited for
applications in radar, imaging, high-speed acquisition, and
communications. A multistage pipelined architecture with
output error correction logic provides for no missing codes
over the full operating temperature range. Internal control
registers are used to program the ADC into the desired
mode. The THS1206 consists of four analog inputs, which
are sampled simultaneously. These inputs can be selected
individually and configured to single-ended or differential
inputs. An integrated 16 word deep FIFO allows the
storage of data in order to take the load off of the processor
connected to the ADC. Internal reference voltages for the
ADC (1.5 V and 3.5 V) are provided.
An external reference can also be chosen to suit the dc
accuracy and temperature drift requirements of the
application. Two different conversion modes can be
selected. In single conversion mode, a single and
simultaneous conversion of up to four inputs can be
initiated by using the single conversion start signal
(CONVST
). The conversion clock in single conversion
mode is generated internally using a clock oscillator
circuit. In continuous conversion mode, an external clock
signal is applied to the CONV_CLK input of the THS1206.
The internal clock oscillator is switched off in continuous
conversion mode.
The THS1206C is characterized for operation from 0°C to
70°C while the THS1206I is characterized for operation
from –40°C to 85°C. The THS1206Q is characterized to
meet the rigorous requirements of the automotive
environment from –40°C to 125°C. The THS1206M is
characterized for operation over the full military
temperature range of –55°C to 125°C.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these
products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 1999 – 2003, Texas Instruments Incorporated
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
2
ORDERING INFORMATION
PACKAGED DEVICE
T
A
TSSOP
(DA)
0°C to 70°C THS1206CDA
–40°C to 85°C THS1206IDA
–40°C to 125°C THS1206QDA
–55°C to 125°C THS1206MDA
These devices have limited built-in ESD protection. The
leads should be shorted together or the device placed in
conductive foam during storage or handling to prevent
electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
THS1206
DGND to DV
DD
–0.3 V to 6.5 V
Supply voltage range
BGND to BV
DD
–0.3 V to 6.5 V
AGND to AV
DD
–0.3 V to 6.5 V
Analog input voltage range AGND –0.3 V to AV
DD
+ 1.5 V
Reference input voltage –0.3 V + AGND to AV
DD
+ 0.3 V
Digital input voltage range –0.3 V to BV
DD
/DV
DD
+ 0.3 V
Operating virtual junction temperature range, T
J
–55°C to 150°C
THS1206C 0°C to 70°C
O
p
erating free air tem
p
erature range T
A
THS1206I –40°C to 85°C
Operating
free
-
air
temperat
u
re
range
,
T
A
THS1206Q –40°C to 125°C
THS1206M –55°C to 125°C
Storage temperature range, T
stg
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
3
RECOMMENDED OPERATING CONDITIONS
POWER SUPPLY MIN NOM MAX UNIT
AV
DD
4.75 5 5.25
Supply voltage
DV
DD
3 3.3 5.25
V
BV
DD
3 3.3 5.25
ANALOG AND REFERENCE INPUTS MIN NOM MAX UNIT
Analog input voltage in single-ended configuration V
REFM
V
REFP
V
Common-mode input voltage V
CM
in differential configuration 1 2.5 4 V
External reference voltage,V
REFP
(optional) 3.5 AV
DD
–1.2 V
External reference voltage, V
REFM
(optional) 1.4 1.5 V
Input voltage difference, REFP – REFM 2 V
DIGITAL INPUTS MIN NOM MAX UNIT
High level in
p
ut voltage V
IH
BV
DD
= 3.3 V 2 V
High
-
le
v
el
inp
u
t
v
oltage
,
V
IH
BV
DD
= 5.25 V 2.6 V
Low level in
p
ut voltage V
IL
BV
DD
= 3.3 V 0.6 V
Lo
w-
le
v
el
inp
u
t
v
oltage
,
V
IL
BV
DD
= 5.25 V 0.6 V
Input CONV_CLK frequency DV
DD
= 3 V to 5.25 V 0.1 6 MHz
CONV_CLK pulse duration, clock high, t
w(CONV_CLKH)
DV
DD
= 3 V to 5.25 V 80 83 5000 ns
CONV_CLK pulse duration, clock low, t
w(CONV_CLKL)
DV
DD
= 3 V to 5.25 V 80 83 5000 ns
THS1206CDA 0 70
O
p
erating free air tem
p
erature T
A
THS1206IDA –40 85
°C
Operating
free
-
air
temperat
u
re
,
T
A
THS1206QDA –40 125
°C
THS1206MDA –55 125
PACKAGE DISSIPATION RATINGS
PACKAGE
T
A
≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE T
A
= 25°C
(1)
T
A
= 70°C
POWER RATING
T
A
= 85°C
POWER RATING
T
A
= 125°C
POWER RATING
DA 1453 mW 11.62 mW/°C 930 mW 756 mW 291 mW
(1)
This is the inverse of the traditional junction-to-ambient thermal resistance (R
θJA
). Thermal resistances are not production tested and are for
informational purposes only.
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
4
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, V
REF
= internal (unless otherwise noted)
DIGITAL SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital inputs
I
IH
High-level input current DV
DD
= digital inputs –50 50 µA
I
IL
Low-level input current Digital input = 0 V –50 50 µA
C
i
Input capacitance 5 pF
Digital outputs
V
OH
High level out
p
ut voltage
BV
DD
–0.5 V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
I
OH
= 50 µA
BV
DD
= 3.3 V
,
BV
DD
–0.5 V
V
OL
Low level out
p
ut voltage
I
OH
= –
50
µ
A
BV
DD
3.3
V,
BV
DD
= 5 V
0.4 V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
0.4 V
I
OZ
High-impedance-state output current CS1 = DGND, CS0 = DV
DD
–10 10 µA
C
O
Output capacitance 5 pF
C
L
Load capacitance at databus D0 – D11 30 pF
DC SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 Bits
Accuracy
Integral nonlinearity INL
C and I suffix ±1.5
LSB
Integral
nonlinearit
y,
INL
Q and M suffix ±1.8
LSB
Differential nonlinearity, DNL ±1 LSB
Offset error
After calibration in single-ended mode 20 LSB
Offset
error
After calibration in differential mode –20 20 LSB
Gain error –20 20 LSB
Analog input
Input capacitance 15 pF
Input leakage current V
AIN
= V
REFM
to V
REFP
±10 µA
Internal voltage reference
Accuracy V
REFP
C and I suffix 3.3 3.5 3.7
V
Acc
u
rac
y,
V
REFP
Q and M suffix
3.3 3.5 3.7
V
Accuracy V
REFM
C and I suffix 1.4 1.5 1.6
V
Acc
u
rac
y,
V
REFM
Q and M suffix
1.3 1.5 1.7
V
Temperature coefficient 50 PPM/°C
Reference noise 100 µV
Accuracy REFOUT
C and I suffix 2.475 2.5 2.525
V
Acc
u
rac
y,
REFOUT
Q and M suffix 2.3 2.5 2.7
V
Power supply
I
DDA
Analog supply current AV
DD
= 5 V, DV
DD
= BV
DD
=3.3 V 36 40 mA
I
DDD
Digital supply current AV
DD
= 5 V, DV
DD
= BV
DD
=3.3 V 0.5 1 mA
I
DDB
Buffer supply current AV
DD
= 5 V, DV
DD
= BV
DD
=3.3 V 1.5 4 mA
I
DD P
Su
pp
ly current in
p
ower down mode
AV
DD
= 5 V
,
C and I suffix 7 mA
I
DD_P
S
u
ppl
y
c
u
rrent
in
po
w
er
-
do
w
n
mode
AV
DD
5
V,
BV
DD
= DV
DD
= 3.3 V
Q and M suffix 10 mA
Power dissipation AV
DD
= 5 V, DV
DD
= BV
DD
= 3.3 V 186 216 mW
Power dissipation in power down AV
DD
= 5 V, DV
DD
= BV
DD
= 3.3 V 30 mW
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
5
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, V
REF
= internal, f
x
= 6 MHz, f
I
= 2 MHz at –1 dBFS (unless otherwise noted)
AC SPECIFICATIONS, AV
DD
= 5 V, BV
DD
= DV
DD
= 3.3 V, C
L
= <30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SINAD
Signal to noise ratio + distortion
Differential mode 63 65 dB
SINAD
Signal
-
to
-
noise
ratio
+
distortion
Single-ended mode
(1)
64 dB
SNR
Signal to noise ratio
Differential mode 64 69 dB
SNR
Signal
-
to
-
noise
ratio
Single-ended mode
(1)
68 dB
Differential mode
C and I suffix –70 –67
THD
Total harmonic distortion
Differential
mode
Q and M suffix –70 –67
dB
THD
Total
harmonic
distortion
Single ended mode
C and I suffix –68
dB
Single
-
ended
mode
Q and M suffix –68
ENOB
Effective number of bits
Differential mode 10.17 11 Bits
(SNR)
Effecti
v
e
n
u
mber
of
bits
Single-ended mode
(1)
10.4 Bits
SFDR
S
p
urious free dynamic range
Differential mode 67 71 dB
SFDR
Sp
u
rio
u
s
free
d
y
namic
range
Single-ended mode 69 dB
Analog Input
Full-power bandwidth with a source impedance of
150 Ω in differential configuration.
FS sinewave, –3 dB 96 MHz
Full-power bandwidth with a source impedance of
150 Ω in single-ended configuration.
FSl sinewave, –3 dB 54 MHz
Small-signal bandwidth with a source impedance of
150 Ω in differential configuration.
100 mVpp sinewave, –3 dB 96 MHz
Small-signal bandwidth with a source impedance of
150 Ω in single-ended configuration.
100 mVpp sinewave, –3 dB 54 MHz
TIMING SPECIFICATIONS
(1)
AV
DD
= 5 V, BV
DD
= DV
DD
= 3.3 V, V
REF
= internal, C
L
< 30 pF
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT
t
d(DATA_AV)
Delay time 5 ns
t
d(o)
Delay time 5 ns
t
pipe
Latency 5
CONV
CLK
(1)
See Figure 25.
剩余42页未读,继续阅读
资源评论
不觉明了
- 粉丝: 3164
- 资源: 5429
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- 基于QT的地图可视化桌面系统后台数据库为MySQL5.7源码.zip
- 基于simulink的PLL锁相环系统仿真【包括模型,文档,参考文献,操作步骤】
- 基于EM-GMM模型的目标跟踪和异常行为检测matlab仿真【包括程序,注释,参考文献,操作步骤,说明文档】
- 2109010044_胡晨燕_选课管理数据库设计与实现.prj
- 帕鲁介绍的PPT备份没什么好下的
- demo1-202405
- 两种方式修改Intel网卡MAC地址
- 服务器搭建所需资源:static文件夹
- Vue02的源码学习资料
- Python 程序语言设计模式思路-行为型模式:访问者模式:在不改变被访问对象结构的情况下,定义对其元素的新操作
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功