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BQ25120F3A 700-nA Low I

Highly Integrated Battery Charge Management Solution

for Wearables and IoT

1 Features

• Increases system operation time between charges

– Configurable 300-mA buck regulator

(1.8-V default)

– 700-nA (typical) Iq with buck converter enabled

(no load)

– Configurable load switch or 100-mA LDO

output (LDO by default. VLDO 1.8-V)

– Up to 300-mA charge current for fast charging.

C programmable up to 200 mA, external

resistor setting for 200 mA to 300 mA.

– 0.5% Accurate battery voltage regulation

(configurable from 3.6 V to 4.65 V in 10-mV

steps) 4.35-V default

– Configurable termination current down to

500 µA

– Simple voltage based battery monitor

– Watchdog timer disabled

– TS WARM fault disabled (no reduction in

battery regulation voltage)

• Highly integrated solution with small footprint

– 2.5-mm x 2.5-mm WCSP Package and six

external components for minimal solution

– Push-button wake-up and reset with adjustable

timers

– Power path management for powering the

system and charging the battery

– Power path management enables <50 nA Ship

Mode battery quiescent current for longest shelf

life

– Battery charger operates from 3.4 V – 5.5 V

(5.5-V OVP / 20-V tolerant)

– Dedicated pins for input current limit, charge

current, termination current, and status output

• I

C communication control

– Charge voltage and current

– Termination threshold

– Input current limit

– VINDPM Threshold

– Timer options

– Load switch control

– System output voltage adjustment

– LDO output voltage adjustment

2 Applications

• Smart watches and other wearable devices

• Fitness accessories

• Health monitoring medical accessories

• Rechargeable toys

3 Description

The BQ25120F3A is a highly integrated battery

charge management IC that integrates the most

common functions for wearable devices: Linear

charger, regulated output, load switch, manual reset

with timer, and battery voltage monitor. The integrated

buck converter is a high efficiency, low I

switcher

using DCS-Control

™

that extends light load efficiency

down to 10-µA load currents. The low quiescent

current during operation and shutdown enables

maximum battery life. The device supports charge

currents from 5 mA to 300 mA.

Device Information

PART NUMBER PACKAGE

(1)

BODY SIZE (NOM)

BQ25120F3A DSBGA (25) 2.50 mm x 2.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

GND

HOST

SDA

SCL

INT

BAT

BQ2512x

MCU /

SYSTEM

NTC

LS / LDO

<100mA

Load

SYS

RESET

LSCTRL

VINLS

Unregulated

Load

PMID

IPRETERM

ISET

ILIM

Simplified Schematic

www.ti.com

BQ25120F3A

SLUSDI4A – OCTOBER 2018 – REVISED APRIL 2021

Submit Document Feedback

Product Folder Links: BQ25120F3A

BQ25120F3A

SLUSDI4A – OCTOBER 2018 – REVISED APRIL 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Device Comparison Table...............................................3

7 Pin Configuration and Functions...................................4

8 Specifications.................................................................. 6

8.1 Absolute Maximum Ratings........................................ 6

8.2 ESD Ratings............................................................... 6

8.3 Recommended Operating Conditions.........................6

8.4 Thermal Information....................................................7

8.5 Electrical Characteristics.............................................8

8.6 Timing Requirements................................................12

8.7 Typical Characteristics..............................................15

9 Detailed Description......................................................17

9.1 Overview................................................................... 17

9.2 Functional Block Diagram......................................... 17

9.3 Feature Description...................................................18

9.4 Device Functional Modes..........................................30

9.5 Programming............................................................ 32

9.6 Register Maps...........................................................35

10 Application and Implementation................................ 48

10.1 Application Information........................................... 48

10.2 Typical Application.................................................. 49

11 Power Supply Recommendations..............................64

12 Layout...........................................................................65

12.1 Layout Guidelines................................................... 65

12.2 Layout Example...................................................... 65

13 Device and Documentation Support..........................66

13.1 Device Support....................................................... 66

13.2 Receiving Notification of Documentation Updates..66

13.3 Trademarks.............................................................66

13.4 Support Resources................................................. 66

13.5 Electrostatic Discharge Caution..............................66

13.6 Glossary..................................................................66

14 Mechanical, Packaging, and Orderable

Information.................................................................... 66

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (October 2018) to Revision A (January 2021) Page

• Changed status from restricted to public............................................................................................................ 1

BQ25120F3A

SLUSDI4A – OCTOBER 2018 – REVISED APRIL 2021

www.ti.com

2 Submit Document Feedback

Product Folder Links: BQ25120F3A

7 Pin Configuration and Functions

GND

RESETINT

IPRETE

ISET

BATBAT

ILIM

VINLS

PGNDSWPMID

1 2 3 4

SDALSCTRLCD SCL

LS/LDO

SYSPMID

GND

Figure 7-1. YFP Package 25-Pin DSBGA Top View

Table 7-1. Pin Functions

I/O DESCRIPTION

NAME NO.

IN A2 I

DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with

at least 1 µF of capacitance using a ceramic capacitor.

PMID A3, B3 I/O

High Side Bypass Connection. Connect at least 3µF of ceramic capacitance with DC bias

derating from PMID to GND as close to the PMID and GND pins as possible. When entering

Ship Mode, PMID is discharged by a 20-kΩ internal discharge resistor.

GND A1, D5 Ground connection. Connect to the ground plane of the circuit.

PGND A5

Power ground connection. Connect to the ground plane of the circuit. Connect the output

filter cap from the buck converter to this ground as shown in the layout example.

CD E2 I

Chip Disable. Drive CD low to place the part in High-Z mode with battery only present, or

enable charging when V

is valid. Drive CD high for Active Battery mode when battery only

is present, and disable charge when V

is present. CD is pulled low internally with 900 kΩ.

SDA E4 I/O I

C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.

SCL E5 I I

C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.

ILIM C2 I

Adjustable Input Current Limit Programming. Connect a resistor from ILIM to GND to

program the input current limit. The input current includes the system load and the battery

charge current. Connect ILIM to GND to set the input current limit to the internal default

threshold. ILIM can also be updated through I

LSCTRL E3 I

Load Switch and LDO Control Input. Pull high to enable the LS/LDO output, pull low to

disable the LS/LDO output.

ISET C1 I

Fast-Charge Current Programming Input. Connect a resistor from ISET to GND to program

the fast-charge current level. Connect a resistor from ISET to GND to set the charge current

to the internal default. ISET can also be updated through I

C. While charging, the voltage

at ISET reflects the actual charging current and can be used to monitor charge current if an

ISET resistor is present and the device is not in host mode.

BQ25120F3A

SLUSDI4A – OCTOBER 2018 – REVISED APRIL 2021

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4 Submit Document Feedback

Product Folder Links: BQ25120F3A

Table 7-1. Pin Functions (continued)

I/O DESCRIPTION

NAME NO.

IPRETERM D1 I

Termination current programming input. Connect a 0-Ω to 10-kΩ resistor from IPRETERM to

GND to program the termination current between 5% and 20% of the charge current. The

pre-charge current is the same as the termination current setting. Connect IPRETERM to

GND to set the termination current to the internal default threshold. IPRETERM can also be

updated through I

INT D2 O

Status Output. INT is an open-drain output that signals charging status and fault interrupts.

INT pulls low during charging. INT is high impedance when charging is complete, disabled,

or the charger is in high impedance mode. When a fault occurs, a 128µs pulse is sent out as

an interrupt for the host. INT charge indicator function is enabled/disabled using the EN_INT

bit in the control register. Connect INT to a logic rail using an LED for visual indication of

charge status or through a 100kΩ resistor to communicate with the host processor.

PG D4 O

Open-drain Power Good status indication output. PG pulls to GND when V

is above

(BAT)

+ V

SLP

and less that V

OVP

. PG is high-impedance when the input power is not within

specified limits. Connect PG to the desired logic voltage rail using a 1kΩ to 100kΩ resistor,

or use with an LED for visual indication. PG can also be configured as a push-button voltage

shifted output (MRS) in the registers, where the output of the

PG pin reflects the status of

the MR input, but pulled up to the desired logic voltage rail using a 1kΩ to 100kΩ resistor.

RESET D3 O

Reset Output. RESET is an open drain active low output that goes low when MR is held

low for longer than t

RESET

, which is configurable by the MRRESET registers. RESET is

deasserted after the t

RESET_D,

typically 400ms.

MR E1 I

Manual Reset Input. MR is a push-button input that must be held low for greater than t

RESET

to assert the reset output. If MR is pressed for a shorter period, there are two programmable

timer events, t

WAKE1

and t

WAKE2

, that trigger an interrupt to the host. The MR input can also

be used to bring the device out of Ship mode.

SW A4 O Inductor Connection. Connect to the switched side of the external inductor.

SYS B5 I

System Voltage Sense Connection. Connect SYS to the system output at the output bulk

capacitors. Bypass SYS locally with at least 4.7 µF of effective ceramic capacitance.

LS/LDO C5 O

Load Switch or LDO output. Connect 1 µF of effective ceramic capacitance to this pin to

assure stability. Be sure to account for capacitance bias voltage derating when selecting the

capacitor.

VINLS B4, C4 I

Input to the Load Switch / LDO output. Connect 1 µF of effective ceramic capacitance from

this pin to GND.

BAT B1, B2 I/O

Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with

at least 1 µF of ceramic capacitance.

TS C3 I

Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from VIN to

GND. The NTC is connected from TS to GND. TS faults are reported by the I

C interface

during charge mode.

www.ti.com

BQ25120F3A

SLUSDI4A – OCTOBER 2018 – REVISED APRIL 2021

Submit Document Feedback

Product Folder Links: BQ25120F3A

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