ddr3中文数据手册Micron-MT4LC16M4G3资源-CSDN文库

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16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

16 MEG x 4 EDO DRAM PART NUMBERS

REFRESH

PART NUMBER ADDRESSING PACKAGE REFRESH

MT4LC16M4H9DJ-x 4K SOJ Standard

MT4LC16M4H9DJ-x S 4K SOJ Self

MT4LC16M4H9TG-x 4K TSOP Standard

MT4LC16M4H9TG-x S 4K TSOP Self

MT4LC16M4G3DJ-x 8K SOJ Standard

MT4LC16M4G3DJ-x S 8K SOJ Self

MT4LC16M4G3TG-x 8K TSOP Standard

MT4LC16M4G3TG-x S 8K TSOP Self

x = speed

FEATURES

• Single +3.3V ±0.3V power supply

• Industry-standard x4 pinout, timing, functions,

and packages

• 12 row, 12 column addresses (H9) or

13 row, 11 column addresses (G3)

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-compat-

ible

• Extended Data-Out (EDO) PAGE MODE access

• Optional self refresh (S) for low-power data

retention

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH

distributed across 64ms

OPTIONS MARKING

• Refresh Addressing

4,096 (4K) rows H9

8,192 (8K) rows G3

• Plastic Packages

32-pin SOJ (400 mil) DJ

32-pin TSOP (400 mil) TG

• Timing

50ns access -5

60ns access -6

• Refresh Rates

Standard Refresh None

Self Refresh (128ms period) S*

NOTE: 1. The 16 Meg x 4 EDO DRAM base number

differentiates the offerings in one place—

MT4LC16M4H9. The fifth field distinguishes the

address offerings: H9 designates 4K addresses and

G3 designates 8K addresses.

2. The “#” symbol indicates signal is active LOW.

*Contact factory for availability

Part Number Example:

MT4LC16M4H9DJ-6

PIN ASSIGNMENT (Top View)

DRAM

MT4LC16M4G3, MT4LC16M4H9

For the latest data sheet, please refer to the Micron Web

site: www.micronsemi.com/mti/msp/html/datasheet.html

32-Pin SOJ 32-Pin TSOP

DQ0

DQ1

WE#

RAS#

Vss

DQ3

DQ2

CAS#

OE#

NC/A12**

A11

A10

Vss

DQ0

DQ1

WE#

RAS#

Vss

DQ3

DQ2

CAS#

OE#

/A12**

A11

A10

Vss

KEY TIMING PARAMETERS

SPEED

RAC

CAC

CAS

-5 84ns 50ns 20ns 25ns 13ns 8ns

-6 104ns 60ns 25ns 30ns 15ns 10ns

**NC on H9 version, A12 on G3 version

GENERAL DESCRIPTION

The 16 Meg x 4 DRAM is a high-speed CMOS,

dynamic random-access memory device containing

67,108,864 bits and designed to operate from 3V to

3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are

functionally organized as 16,777,216 locations con-

taining 4 bits each. The 16,777,216 memory locations

are arranged in 4,096 rows by 4,096 columns on the H9

version and 8,192 rows by 2,048 columns on the G3

version. During READ or WRITE cycles, each location is

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

uniquely addressed via the address bits. First, the row

address is latched by the RAS# signal, then the column

address is latched by CAS#. The device provides EDO-

PAGE-MODE operation, allowing for fast successive

data operations (READ, WRITE, or READ-MODIFY-

WRITE) within a given row.

The 16 Meg x 4 DRAM must be refreshed periodically

in order to retain stored data.

DRAM ACCESS

Each location in the DRAM is uniquely addressable,

as mentioned in the General Description. The data for

each location is accessed via the four I/O pins (DQ0-

DQ3). A logic HIGH on WE# dictates read mode, while

a logic LOW on WE# dictates write mode. During a

WRITE cycle, data-in (D) is latched by the falling edge

of WE# or CAS#, whichever occurs last. An EARLY

WRITE occurs when WE# is taken LOW prior to CAS#

falling. A LATE WRITE or READ-MODIFY-WRITE occurs

when WE# falls after CAS# is taken LOW. During

EARLY WRITE cycles, the data outputs (Q) will remain

High-Z, regardless of the state of OE#. During LATE

WRITE or READ-MODIFY-WRITE cycles, OE# must be

taken HIGH to disable the data outputs prior to apply-

ing input data. If a LATE WRITE or READ-MODIFY-

WRITE is attempted while keeping OE# LOW, no WRITE

will occur, and the data outputs will drive read data

from the accessed location.

EDO PAGE MODE

DRAM READ cycles have traditionally turned the

output buffers off (High-Z) with the rising edge of

CAS#. If CAS# went HIGH and OE# was LOW (active),

the output buffers would be disabled. The 16 Meg x 4

DRAM offers an accelerated page mode cycle by elimi-

nating output disable from CAS# HIGH. This option is

called EDO and it allows CAS# precharge time (

CP) to

occur without the output data going invalid (see READ

and EDO-PAGE-MODE READ waveforms).

EDO operates like any DRAM READ or FAST-PAGE-

MODE READ, except data is held valid after CAS# goes

HIGH, as long as RAS# and OE# are held LOW and WE#

is held HIGH. OE# can be brought LOW or HIGH while

CAS# and RAS# are LOW, and the DQs will transition

between valid data and High-Z. Using OE#, there are

two methods to disable the outputs and keep them

disabled during the CAS# HIGH time. The first method

is to have OE# HIGH when CAS# transitions HIGH and

keep OE# HIGH for

OEHC thereafter. This will disable

the DQs, and they will remain disabled (regardless of

the state of OE# after that point) until CAS# falls again.

The second method is to have OE# LOW when CAS#

transitions HIGH and then bring OE# HIGH for a

minimum of

OEP anytime during the CAS# HIGH

period. This will disable the DQs, and they will remain

disabled (regardless of the state of OE# after that point)

until CAS# falls again. (Please refer to Figure 1.) During

other cycles, the outputs are disabled at

OFF time after

RAS# and CAS# are HIGH or at

WHZ after WE# transi-

tions LOW. The

OFF time is referenced from the rising

edge of RAS# or CAS#, whichever occurs last. WE# can

also perform the function of disabling the output

drivers under certain conditions, as shown in Figure 2.

EDO-PAGE-MODE operations are always initiated

with a row address strobed in by the RAS# signal,

followed by a column address strobed in by CAS#, just

like for single location accesses. However, subsequent

column locations within the row may then be accessed

at the page mode cycle time. This is accomplished by

cycling CAS# while holding RAS# LOW and entering

new column addresses with each CAS# cycle. Returning

RAS# HIGH terminates the EDO-PAGE-MODE opera-

tion.

DRAM REFRESH

The supply voltage must be maintained at the speci-

fied levels, and the refresh requirements must be met in

order to retain stored data in the DRAM. The refresh

requirements are met by refreshing all 8,192 rows (G3)

or all 4,096 rows (H9) in the DRAM array at least once

every 64ms. The recommended procedure is to execute

4,096 CBR REFRESH cycles, either uniformly spaced or

grouped in bursts, every 64ms. The MT4LC16M4G3

internally refreshes two rows for every CBR cycle,

whereas the MT4LC16M4H9 refreshes one row for

every CBR cycle. So with either device, executing 4,096

CBR cycles covers all rows. The CBR refresh will invoke

the internal refresh counter for automatic RAS# ad-

dressing. Alternatively, RAS#-ONLY REFRESH capabil-

ity is inherently provided. However, with this method,

some compatibility issues may become apparent. For

example, both G3 and H9 versions require 4,096 CBR

REFRESH cycles, yet each requires a different number of

RAS#-ONLY REFRESH cycles (G3 = 8,192 and H9 =

4,096). JEDEC strongly recommends the use of CBR

REFRESH for this device.

An optional self refresh mode is also available on the

“S” version. The self refresh feature is initiated by

performing a CBR REFRESH cycle and holding RAS#

LOW for the specified

RASS. The “S” option allows for

an extended refresh period of 128ms, or 31.25µs per

row for a 4K refresh and 15.625µs per row for an 8K

refresh, when using a distributed CBR REFRESH. This

refresh rate can be applied during normal operation, as

well as during a standby or battery backup mode.

GENERAL DESCRIPTION (Continued)

剩余22页未读，继续阅读

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