ddr3中文数据手册Micron-MT4C1M16C3资源-CSDN文库

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1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

FPM DRAM

MT4C1M16C3, MT4LC1M16C3

For the latest data sheet revisions, please refer to the Micron

Web site: www.micron.com/datasheets

FPM DRAM

PIN ASSIGNMENT (Top View)

FEATURES

• JEDEC- and industry-standard x16 timing,

functions, pinouts, and packages

• High-performance, low-power CMOS silicon-gate

process

• Single power supply (+3.3V ±0.3V or 5V ±0.5V)

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

• Optional self refresh (S) for low-power data

retention

• BYTE WRITE and BYTE READ access cycles

• 1,024-cycle refresh (10 row, 10 column addresses)

• FAST-PAGE-MODE (FPM) access

OPTIONS MARKING

• Voltage

3.3V LC

5V C

• Packages

Plastic SOJ (400 mil) DJ

Plastic TSOP (400 mil) TG

• Timing

50ns access -5

60ns access -6

• Refresh Rates

Standard Refresh (16ms period) None

Self Refresh (128ms period) S

• Operating Temperature Range

Commercial (0

C to +70

C) None

Extended (-20

C to +80

C) ET

Part Number Example:

MT4LC1M16C3DJ-5

NOTE: 1. The third field distinguishes the low voltage offering:

LC designates VCC = 3.3V and C designates VCC = 5V.

2. Contact factory for availability.

3. Available only on MT4C1M16C3 (5V)

1 MEG x 16 FPM DRAM PART NUMBERS

PART NUMBER SUPPLY PACKAGE REFRESH

MT4LC1M16C3DJ-6 3.3V SOJ Standard

MT4LC1M16C3DJ-6 S 3.3V SOJ Self

MT4LC1M16C3TG-6 3.3V TSOP Standard

MT4LC1M16C3TG-6 S 3.3V TSOP Self

MT4C1M16C3DJ-6 5V SOJ Standard

MT4C1M16C3TG-6 5V TSOP Standard

GENERAL DESCRIPTION

The 1 Meg x 16 DRAM is a randomly accessed, solid-

state memory containing 16,777,216 bits organized in

a x16 configuration. The 1 Meg x 16 DRAM has both

BYTE WRITE and WORD WRITE access cycles via two

CAS# pins (CASL# and CASH#). These function identi-

cally to a single CAS# on other DRAMs in that either

CASL# or CASH# will generate an internal CAS#.

The CAS# function and timing are determined by

the first CAS# (CASL# or CASH#) to transition LOW and

44/50-Pin TSOP

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

WE#

RAS#

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

CASL#

CASH#

OE#

42-Pin SOJ

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

WE#

RAS#

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

CASL#

CASH#

OE#

NOTE: The # symbol indicates signal is active LOW.

KEY TIMING PARAMETERS

SPEED

RAC

CAC

-5 84ns 50ns 20ns 25ns 15ns 30ns

-6 110ns 60ns 35ns 30ns 15ns 40ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

FPM DRAM

the last CAS# to transition back HIGH. Use of only one

of the two results in a BYTE access cycle. CASL#

transitioning LOW selects an access cycle for the lower

byte (DQ0-DQ7), and CASH# transitioning LOW se-

lects an access cycle for the upper byte (DQ8-DQ15).

Each bit is uniquely addressed through the 20 ad-

dress bits during READ or WRITE cycles. These are

entered ten bits (A0-A9) at a time. RAS# is used to latch

the first ten bits and CAS# the latter ten bits. The CAS#

function is determined by the first CAS# (CASL# or

CASH#) to transition LOW and the last one to transition

back HIGH. The CAS# function also determines

whether the cycle will be a refresh cycle (RAS#-ONLY)

or an active cycle (READ, WRITE, or READ-WRITE) once

RAS# goes LOW.

The CASL# and CASH# inputs internally generate a

CAS# signal that functions identically to a single CAS#

input on other DRAMs. The key difference is that each

CAS# input (CASL# and CASH#) controls its corre-

GENERAL DESCRIPTION (continued)

sponding DQ tristate logic (in conjunction with OE#

and WE#). CASL# controls DQ0-DQ7 and CASH# con-

trols DQ8-DQ15. The two CAS# controls give the

1 Meg x 16 DRAM BYTE WRITE cycle capabilities.

A logic HIGH on WE# dictates read mode, while a

logic LOW on WE# dictates write mode. During a WRITE

cycle, data-in (D) is latched by the falling edge of WE#

or CAS, whichever occurs last. Taking WE# LOW will

initiate a WRITE cycle, selecting DQ0-DQ15. If WE#

goes LOW prior to CAS# going LOW, the output pin(s)

remain open (High-Z) until the next CAS# cycle. If WE#

goes LOW after CAS# goes LOW and data reaches the

output pins, data-out (Q) is activated and retains the

selected cell data as long as CAS# and OE# remain LOW

(regardless of WE# or RAS#). This late WE# pulse re-

sults in a READ-WRITE cycle.

The 16 data inputs and 16 data outputs are routed

through 16 pins using common I/O. Pin direction is

controlled by OE# and WE#.

CASL#

CAS#

RAS#

NO. 2 CLOCK

GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR

1,024 x 1,024 x 16

MEMORY

ARRAY

VDD

VSS

OE#

DQ0

DQ15

REFRESH

COUNTER

CASH#

1,024

1,024 x 16

SENSE AMPLIFIERS

I/O GATING

1,024

DATA-OUT

BUFFER

WE#

ROW-

ADDRESS

BUFFERS (10)

ROW

DECODER

COLUMN-

ADDRESS

BUFFER

DATA-IN BUFFER

COLUMN

DECODER

FUNCTIONAL BLOCK DIAGRAM

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

FPM DRAM

GENERAL DESCRIPTION (continued)

The MT4LC1M16C3 must be refreshed periodically

in order to retain stored data.

FAST PAGE MODE ACCESS

FAST-PAGE-MODE operations allow faster data op-

erations (READ, WRITE or READ-MODIFY-WRITE)

within a row-address-defined (A0-A9) page boundary.

The FAST-PAGE-MODE cycle is always initiated with a

row address strobed in by RAS#, followed by a column

address strobed in by CAS#. Additional columns may

be accessed by providing valid column addresses,

strobing CAS# and holding RAS# LOW, thus executing

faster memory cycles. Returning RAS# HIGH termi-

nates the FAST-PAGE-MODE operation.

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced

standbylevel. The chip is also preconditioned for the

next cycle during the RAS# HIGH time. Memory cell

data is retained in its correct state by maintaining power

and executing anyRAS# cycle (READ, WRITE) or RAS#

REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that

all 1,024 combinations of RAS# addresses (A0-A9) are

executed at least every 16ms (128ms on the “S” ver-

sion), regardless of sequence. The CBR REFRESH cycle

will also invoke the refresh counter and controller for

row-address control.

BYTE ACCESS CYCLE

The BYTE WRITEs and BYTE READs are determined

by the use of CASL# and CASH#. Enabling CASL# will

select a lower byte access (DQ0-DQ7), while enabling

CASH# will select an upper byte access (DQ0-DQ15).

Enabling both CASL# and CASH# selects a WORD

WRITE cycle.

The 1 Meg x 16 DRAM may be viewed as two 1 Meg x

8 DRAMs that have common input controls, with the

exception of the CAS# inputs. Figure 1 illustrates the

BYTE WRITE and WORD WRITE cycles. Figure 2 illus-

trates BYTE READ and WORD READ cycles.

Figure 1

WORD and BYTE WRITE Example

STORED

DATA

RAS#

CASL#

WE#

X = NOT EFFECTIVE (DON'T CARE)

ADDRESS 1

ADDRESS 0

WORD WRITE LOWER BYTE WRITE

CASH#

INPUT

DATA

INPUT

DATA

INPUT

DATA

STORED

DATA

INPUT

DATA

STORED

DATA

STORED

DATA

UPPER BYTE

(DQ8-DQ15)

OF WORD

LOWER BYTE

(DQ0-DQ7)

OF WORD

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

FPM DRAM

STORED

DATA

RAS#

CASL#

WE#

Z = High-Z

ADDRESS 1ADDRESS 0

WORD READ LOWER BYTE READ

STORED

DATA

CASH#

OUTPUT

DATA

STORED

DATA

OUTPUT

DATA

OUTPUT

DATA

OUTPUT

DATA

STORED

DATA

UPPER BYTE

(DQ8-DQ15)

OF WORD

LOWER BYTE

(DQ0-DQ7)

OF WORD

Additionally, both bytes must always be of the same

mode of operation if both bytes are active. A CAS#

precharge must be satisfied prior to changing modes of

operation between the upper and lower bytes. For ex-

ample, an EARLY WRITE on one byte and a LATE WRITE

on the other byte are not allowed during the same cycle.

However, an EARLY WRITE on one byte and a LATE

WRITE on the other byte, after a CAS# precharge has

been satisfied, are permissible.

DRAM REFRESH

Preserve correct memory cell data by maintaining

power and executing any RAS# cycle (READ, WRITE) or

RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)

so that all 1,024 combinations of RAS# addresses are

executed within

REF (MAX), regardless of sequence.

The CBR and EXTENDED and SELF REFRESH cycles

will invoke the internal refresh counter for automatic

RAS# addressing.

An optional self refresh mode is available on the “S”

version. The self refresh feature is initiated by per-

forming a CBR REFRESH cycle and holding RAS# LOW

for the specified

RASS. The “S” option allows the user

the choice of a fully static, low-power data retention

mode or a dynamic refresh mode at the extended re-

fresh period of 128ms, or 125µs per row, when using a

distributed CBR REFRESH. This refresh rate can be

applied during normal operation, as well as during a

standby or battery backup mode.

The self refresh mode is terminated by driving

RAS# HIGH for a minimum time of

RPS. This delay

allows for the completion of any internal refresh cycles

that may be in process at the time of the RAS# LOW-

to-HIGH transition. If the DRAM controller uses a dis-

tributed CBR refresh sequence, a burst refresh is not

required upon exiting self refresh. However, if the

DRAM controller utilizes a RAS#-ONLY or burst CBR

refresh sequence, all 1,024 rows must be refreshed us-

ing a minimum

RC refresh rate prior to resuming nor-

mal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced

standby level. The chip is preconditioned for the next

cycle during the RAS# HIGH time.

Figure 2

WORD and BYTE READ Example

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

FPM DRAM

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX)

3.3V 5V

PARAMETER/CONDITION SYMBOL MIN MAX MIN MAX UNITS NOTES

SUPPLY VOLTAGE VCC 3 3.6 4.5 5.5 V

INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC VIH 2 5.5 2.4 VCC + 1 V

INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC VIL -1.0 0.8 -0.5 0.8 V

INPUT LEAKAGE CURRENT:

Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); II -2 2 -2 2 µA

All other pins not under test = 0V

OUTPUT HIGH VOLTAGE:

IOUT = -2mA VOH 2.4 – 2.4 – V

OUTPUT LOW VOLTAGE:

IOUT = 2mA VOL – 0.4 – 0.4 V

OUTPUT LEAKAGE CURRENT:

Any output at VOUT [0V ≤ VOUT ≤ VCC (MAX)]; IOZ -5 5 -5 5 µA

DQ is disabled and in High-Z state

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Pin Relative to VSS

3.3V ..................................................... -1V to +4.6V

5V ........................................................... -1V TO +7V

Voltage on NC, Inputs or I/O Pins Relative to V

3.3V ..................................................... -1V to +5.5V

5V ........................................................... -1V TO +7V

Operating Temperature

(commercial) ...................................... 0°C to +70°C

(extended "ET") ............................ -20°C to +80°C

Storage Temperature (plastic) ............ -55°C to +150°C

Power Dissipation ........................................................ 1W

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

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