ddr3中文数据手册Micron-MT4C16270_ddr3器件手册资源-CSDN文库

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MT4C16270 Micron Technology, Inc., reserves the right to change products or specifications without notice.

W06.pm5 – Rev. 10/96 1996, Micron Technology, Inc.

MT4C16270

256K x 16 DRAM

TECHNOLOGY, INC.

DRAM 256K x 16 DRAM

5V, EDO PAGE MODE

FEATURES

• Industry-standard x16 pinouts, timing, functions

and packages

• High-performance CMOS silicon-gate process

• Single +5V ±10% power supply*

• Low power, 3mW standby; 300mW active, typical

• All device pins are TTL-compatible

• 512-cycle refresh in 8ms (9 row- and 9 column

addresses)

• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

• Extended Data-Out (EDO) PAGE MODE access cycle

• BYTE WRITE and BYTE READ access cycles

OPTIONS MARKING

• Timing

40ns access -4*

50ns access -5*

60ns access -6

• Packages

Plastic SOJ (400 mil) DJ

• Part Number Example: MT4C16270DJ-4

*40ns and 50ns access specifications are limited to a VCC range of ±5%.

Contact factory for availability.

PIN ASSIGNMENT (Top View)

40-Pin SOJ

(DA-6)

Vcc

DQ1

DQ2

DQ3

DQ4

Vcc

DQ5

DQ6

DQ7

DQ8

NC

WE#

RAS#

NC

A0

A1

A2

A3

Vcc

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

Vss

DQ16

DQ15

DQ14

DQ13

Vss

DQ12

DQ11

DQ10

DQ9

NC

CASL#

CASH#

OE#

A8

A7

A6

A5

A4

Vss

KEY TIMING PARAMETERS

SPEED

RAC

CAC

CAS

-4 75ns 40ns 15ns 20ns 12ns 6ns 6ns

-5 100ns 50ns 20ns 25ns 15ns 8ns 8ns

-6 110ns 60ns 25ns 30ns 15ns 10ns 10ns

CASL# or CASH# will generate an internal CAS#. Use of

only one of the two results in a BYTE WRITE cycle. CASL#

transitioning LOW selects a WRITE cycle for the lower

byte (DQ1-DQ8) and CASH# transitioning LOW selects a

WRITE cycle for the upper byte (DQ9-DQ16). BYTE READ

cycles are achieved through CASL# or CASH# in the same

manner.

GENERAL DESCRIPTION

The MT4C16270 is a randomly accessed solid-state

memory containing 4,194,304 bits organized in a x16 con-

figuration. The MT4C16270 has both BYTE WRITE and

WORD WRITE access cycles via two CAS# pins.

The MT4C16270 CAS# function and timing are deter-

mined by the first CAS# (CASL# or CASH#) to transition

LOW and by the last to transition back HIGH. CASL# and

CASH# function in a similar manner to CAS# in that either

MT4C16270 Micron Technology, Inc., reserves the right to change products or specifications without notice.

W06.pm5 – Rev. 10/96 1996, Micron Technology, Inc.

MT4C16270

256K x 16 DRAM

TECHNOLOGY, INC.

FUNCTIONAL BLOCK DIAGRAM

CASL#

CAS#

RAS#

NO. 2 CLOCK

GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR

512 x 512 x 16

MEMORY

ARRAY

Vcc

Vss

OE#

DQ1



DQ16

REFRESH

COUNTER

CASH#

A0

A1

A2

A3

A4

A5

A6

A7

512

512 x 16

512

WE#

CONTROL

LOGIC

SENSE AMPLIFIERS

I/O GATING

DATA-OUT

BUFFER

DATA-IN BUFFER

COLUMN-

ADDRESS

BUFFER

ROW-

ADDRESS

BUFFERS (9)

ROW

DECODER

COLUMN

DECODER

FUNCTIONAL DESCRIPTION

Each bit is uniquely addressed through the 18 address

bits during READ or WRITE cycles. These are entered 9 bits

(A0-A8) at a time. RAS# is used to latch the first 9 bits and

CAS# the latter 9 bits.

The CAS# control also determines whether the cycle will

be a refresh cycle (RAS#-ONLY) or an active cycle (READ,

WRITE or READ WRITE) once RAS# goes LOW. The

MT4C16270 has two CAS# controls, CASL# and CASH#.

The CASL# and CASH# inputs internally generate a

CAS# signal functioning in a similar manner to the single

CAS# input on the other 256K x 16 DRAMs. The key

difference is that each CAS# controls its corresponding DQ

tristate logic (in conjunction with OE# and WE# and RAS#).

CASL# controls DQ1 through DQ8 and CASH# controls

DQ9 through DQ16.

The MT4C16270 CAS# function is determined by the first

CAS# (CASL# or CASH# ) transitioning LOW and the last

transitioning back HIGH. The two CAS# controls give the

MT4C16270 both byte READ and byte WRITE cycle capa-

bilities. (See Figure 2.)

A logic HIGH on WE# dictates READ mode while a logic

LOW on WE# dictates WRITE mode. During a WRITE

cycle, data-in (D) is latched by the falling edge of WE or

CAS# (CASL# or CASH#), whichever occurs last. An EARLY

WRITE occurs when WE is taken LOW prior to either CAS#

falling. A LATE WRITE or READ-MODIFY-WRITE occurs

when WE falls after CAS# (CASL# or CASH#) was taken

LOW. During EARLY WRITE cycles, the data-outputs (Q)

will remain High-Z regardless of the state of OE#. During

LATE WRITE or READ-MODIFY-WRITE cycles, OE# must

MT4C16270 Micron Technology, Inc., reserves the right to change products or specifications without notice.

W06.pm5 – Rev. 10/96 1996, Micron Technology, Inc.

MT4C16270

256K x 16 DRAM

TECHNOLOGY, INC.

FUNCTIONAL DESCRIPTION (continued)

be taken HIGH to disable the data-outputs prior to apply-

ing input data. If a LATE WRITE or READ-MODIFY-

WRITE is attempted while keeping OE# LOW, no write will

occur, and the data-outputs will drive read data from the

accessed location.

Additionally, both bytes must always be of the same

mode of operation if both bytes are active. A CAS# precharge

must be satisfied prior to changing modes of operation

between the upper and lower bytes. For example, an EARLY

WRITE on one byte and a LATE WRITE on the other byte is

not allowed during the same cycle. However, an EARLY

WRITE on one byte and, after a CAS# precharge has been

satisfied, a LATE WRITE on the other byte is permissable.

The 16 data inputs and 16 data outputs are routed through

16 pins using common I/O, and pin direction is controlled

by OE#, WE# and RAS#.

EDO PAGE MODE operations allow faster data opera-

tions (READ, WRITE or READ-MODIFY-WRITE) within a

row-address-defined (A0-A8) page boundary. The EDO

PAGE MODE cycle is always initiated with a row address

strobed-in by RAS# followed by a column address

strobed-in by CAS#. CAS# may be toggled by holding

RAS# LOW and strobing-in different column-addresses,

thus executing faster memory cycles. Returning RAS# HIGH

terminates the EDO PAGE MODE operation.

BYTE ACCESS CYCLE

The BYTE WRITE cycle is determined by the use of

CASL# and CASH#. Enabling CASL# will select a lower

BYTE WRITE cycle (DQ1-DQ8) while enabling CASH# will

select an upper BYTE WRITE cycle (DQ9-DQ16). Enabling

both CASL# and CASH# selects a WORD WRITE cycle.

The MT4C16270 can be viewed as two 256K x 8 DRAMs

which have common input controls. Figure 1 illustrates the

MT4C16270 BYTE WRITE and WORD WRITE cycles. The

BYTE READ is accomplished in the same manner.





V

IH

CASL#/CASH#

V

IH

RAS#

V

IH

ADDR



ROW





COLUMN (A)







COLUMN (B)







DON’T CARE

UNDEFINED





V

IH

OE#

V

IOH

IOL

OPEN

VALID DATA (B)

VALID DATA (A)



COLUMN (C)



VALID DATA (A)



VALID DATA (C)



COLUMN (D)







VALID DATA (D)

OEHC

OEP

OES

The DQs go back to

Low-Z if

OES is met.

The DQs remain High-Z

until the next CAS# cycle

OEHC is met.

The DQs remain High-Z

until the next CAS# cycle

OEP is met.

Figure 3

OUTPUT ENABLE AND DISABLE

MT4C16270 Micron Technology, Inc., reserves the right to change products or specifications without notice.

W06.pm5 – Rev. 10/96 1996, Micron Technology, Inc.

MT4C16270

256K x 16 DRAM

TECHNOLOGY, INC.



V

IH

V

IH

RAS#

V

IH

ADDR



ROW





COLUMN (A)







DON’T CARE

UNDEFINED



V

IH

WE#

V

IOH

IOL

OPEN







WPZ

The DQs go to High-Z if WE# falls, and if

WPZ is met, 

will remain High-Z until CAS# goes LOW with 

WE# HIGH (i.e., until a READ cycle is initiated).

V

IH

OE#



VALID DATA (B)

WHZ

WE# may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS# goes LOW with 

WE# HIGH (i.e., until a READ cycle is initiated).



WHZ

COLUMN (D)





VALID DATA (A)

COLUMN (B)

COLUMN (C)

INPUT DATA (C)

CASL#/CASH#

Figure 4

OUTPUT ENABLE AND DISABLE WITH WE#

transitions HIGH. Then OE# can pulse HIGH for a mini-

mum of

OEP anytime during the CAS# HIGH period and

the DQs will tristate and remain tristate, regardless of OE#,

until CAS# falls again (please reference Figure 3 for further

detail on the toggling OE# condition). During other cycles,

the outputs are disabled at

OFF time after RAS# and CAS#

are HIGH, or

WHZ after WE# transitions LOW. The

OFF

time is referenced from the rising edge of RAS# or CAS#,

whichever occurs last. WE# can also perform the function

of turning off the output drivers under certain conditions,

as shown in Figure 4.

Returning RAS# and CAS# HIGH terminates a memory

cycle and decreases chip current to a reduced standby level.

The chip is also preconditioned for the next cycle during the

RAS# HIGH time. Memory cell data is retained in its correct

state by maintaining power and executing any RAS# cycle

(READ, WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR,

or HIDDEN) so that all 512 combinations of RAS# ad-

dresses (A0-A8) are executed at least every 8ms, regardless

of sequence. The CBR REFRESH cycle will also invoke the

refresh counter and controller for row address control.

EDO PAGE MODE

DRAM READ cycles have traditionally turned the out-

put buffers off (High-Z) with the rising edge of CAS#. If

CAS# goes HIGH, and OE# is LOW (active), the output

buffers will be disabled. The MT4C16270 offers an acceler-

ated PAGE MODE cycle by eliminating output disable from

CAS# HIGH. This option is called EDO and it allows CAS#

precharge time (

CP) to occur without the output data going

invalid (see READ and EDO-PAGE-MODE READ wave-

forms).

EDO operates as any DRAM READ or FAST-PAGE-

MODE READ, except data will be held valid after CAS#

goes HIGH, as long as RAS# and OE# are held LOW and

WE# is held HIGH. OE# can be brought LOW or HIGH

while CAS# and RAS# are LOW, and the DQs will transi-

tion between valid data and High-Z. Using OE#, there are

two methods to disable the outputs and keep them disabled

during the CAS# HIGH time. The first method is to have

OE# HIGH when CAS# transitions HIGH and keep OE#

HIGH for

OEHC. This will tristate the DQs and they will

remain tristate, regardless of OE#, until CAS# falls again.

The second method is to have OE# LOW when CAS#

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