ddr3中文数据手册MICRON-MT4LC8M8B6DJ-5S_ddr3数据手册资源-CSDN文库

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8 Meg x 8 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

8 MEG x 8

FPM DRAM

FEATURES

• Single +3.3V ±0.3V power supply

• Industry-standard x8 pinout, timing, functions,

and packages

• 13 row, 10 column addresses (E1) or

12 row, 11 column addresses (B6)

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-

compatible

• FAST PAGE MODE (FPM) access

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH

distributed across 64ms

• Optional self refresh (S) for low-power data

retention

OPTIONS MARKING

• Refresh Addressing

4,096 (4K) rows B6

8,192 (8K) rows E1

• Plastic Packages

32-pin SOJ (400 mil) DJ

32-pin TSOP (400 mil) TG

• Timing

50ns access -5

60ns access -6

• Refresh Rates

Standard Refresh (64ms period) None

Self Refresh (128ms period) S*

NOTE: 1. The 8 Meg x 8 FPM DRAM base number

differentiates the offerings in one place—

MT4LC8M8E1. The fifth field distinguishes

various options: E1 designates an 8K refresh and

B6 designates a 4K refresh for FPM DRAMs.

2. The # symbol indicates signal is active LOW.

*Contact factory for availability

Part Number Example:

MT4LC8M8E1DJ-5

DRAM

MT4LC8M8E1, MT4LC8M8B6

For the latest data sheet, please refer to the Micron Web

site: www.micron.com/products/datasheets/dramds.html

8 MEG x 8 FPM DRAM PART NUMBERS

REFRESH

PART NUMBER ADDRESSING PACKAGE REFRESH

MT4LC8M8E1DJ-x 8K SOJ Standard

MT4LC8M8E1DJ-x S 8K SOJ Self

MT4LC8M8E1TG-x 8K TSOP Standard

MT4LC8M8E1TG-x S 8K TSOP Self

MT4LC8M8B6DJ-x 4K SOJ Standard

MT4LC8M8B6DJ-x S 4K SOJ Self

MT4LC8M8B6TG-x 4K TSOP Standard

MT4LC8M8B6TG-x S 4K TSOP Self

x = speed

**A12 on E1 version, NC on B6 version

32-Pin TSOP

DQ0

DQ1

DQ2

DQ3

WE#

RAS#

DQ7

DQ6

DQ5

DQ4

CAS#

OE#

NC/A12**

A11

A10

32-Pin SOJ

DQ0

DQ1

DQ2

DQ3

WE#

RAS#

DQ7

DQ6

DQ5

DQ4

Vss

CAS#

OE#

/A12**

A11

A10

PIN ASSIGNMENT (Top View)

KEY TIMING PARAMETERS

SPEED

RAC

CAC

-5 90ns 50ns 30ns 25ns 13ns

-6 110ns 60ns 35ns 30ns 15ns

GENERAL DESCRIPTION

The 8 Meg x 8 DRAMs are high-speed CMOS, dy-

namic random-access memory devices containing

67,108,864 bits organized in a x8 configuration. The

8 Meg x 8 DRAMs are functionally organized as 8,388,608

locations containing eight bits each. The 8,388,608

memory locations are arranged in 8,192 rows by 1,024

columns for the MT4LC8M8E1 or 4,096 rows by 2,048

columns for the MT4LC8M8B6. During READ or WRITE

cycles, each location is uniquely addressed via the

address bits. First, the row address is latched by the

8 Meg x 8 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

8 MEG x 8

FPM DRAM

RAS# signal, then the column address by CAS#. Both

devices provide FAST-PAGE-MODE operation, allow-

ing for fast successive data operations (READ, WRITE,

or READ-MODIFY-WRITE) within a given row.

The MT4LC8M8E1 and MT4LC8M8B6 must be re-

freshed periodically in order to retain stored data.

FAST PAGE MODE ACCESS

Each location in the DRAM is uniquely addressable

as mentioned in the General Description. The data for

each location is accessed via the eight I/O pins (DQ0-

DQ7). The WE# signal must be activated to execute a

WRITE operation; otherwise, a READ operation will be

performed. The OE# signal must be activated to enable

the DQ output drivers for a read access and can be

deactivated to disable output data if necessary.

FAST-PAGE-MODE operations are always initiated

with a row address strobed in by the RAS# signal,

followed by a column address strobed in by CAS#, just

like for single location accesses. However, subsequent

column locations within the row may then be accessed

at the page mode cycle time. This is accomplished by

cycling CAS# while holding RAS# LOW and entering

new column addresses with each CAS# cycle. Returning

RAS# HIGH terminates the FAST-PAGE-MODE opera-

tion.

DRAM REFRESH

The supply voltage must be maintained at the speci-

fied levels, and the refresh requirements must be met in

order to retain stored data in the DRAM. The refresh

requirements are met by refreshing all 8,192 rows (E1)

or all 4,096 rows (B6) in the DRAM array at least once

every 64ms. The recommended procedure is to execute

4,096 CBR REFRESH cycles, either uniformly spaced or

grouped in bursts, every 64ms. The MT4LC8M8E1 in-

ternally refreshes two rows for every CBR cycle, whereas

the MT4LC8M8B6 refreshes one row for every CBR

cycle. So with either device, executing 4,096 CBR cycles

covers all rows. The CBR REFRESH cycle will invoke the

internal refresh counter for automatic RAS# address-

ing. Alternatively, RAS#-ONLY REFRESH capability is

inherently provided. However, with this method only

one row is refreshed at a time; so for the MT4LC8M8E1,

8,192 RAS#-ONLY REFRESH cycles must be executed

every 64ms to cover all rows. Some compatibility issues

may become apparent. JEDEC strongly recommends

the use of CBR REFRESH for this device.

An optional self refresh mode is also available on the

“S” version. The self refresh feature is initiated by

performing a CBR REFRESH cycle and holding RAS#

LOW for the specified

RASS. The “S” option allows for

an extended refresh period of 128ms, or 31.25µs per

row for a 4K refresh and 15.625µs per row for an 8K

refresh when using a distributed CBR REFRESH. This

refresh rate can be applied during normal operation, as

well as during a standby or battery backup mode.

The self refresh mode is terminated by driving RAS#

HIGH for a minimum time of

RPS. This delay allows for

the completion of any internal refresh cycles that may

be in process at the time of the RAS# LOW-to-HIGH

transition. If the DRAM controller uses a distributed

CBR refresh sequence, a burst refresh is not required

upon exiting self refresh. However, if the DRAM con-

troller utilizes RAS#-ONLY or burst CBR refresh se-

quence, all rows must be refreshed with a refresh rate of

RC minimum prior to the resumption of normal

operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced

standby level. The chip is preconditioned for the next

cycle during the RAS# HIGH time.

GENERAL DESCRIPTION (continued)

剩余19页未读，继续阅读

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