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TI-TPS23753.pdf
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TI-TPS23753.pdf
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TPS23753
M1
R
CS
C
OUT
D
VC
GATE
RTN
V
C
CS
C
VC
CTL
V
B
D1
58V
C1
0.1µF
R
DEN
R
CLS
From Ethernet
Transformers
V
DD1
V
SS
CLS
C
IN
V
OUT
R
CTL
C
CTL
From Spare
Pairs or
Transformers
D
S
DEN
BLNK
FRS
D
A
R
FRS
V
B
C
VB
Adapter
R
FBU
R
FBL
TLV431
R
OB
C
IZ
APD
R
APD2
R
APD1
R
BLNK
V
DD
C
IO
T1
BR1
BR2
R
VC
* AdapterinterfaceandR
BLNK
areOptional
*
*
TPS23753
www.ti.com
SLVS853C –JUNE 2008–REVISED JANUARY 2010
IEEE 802.3 PoE INTERFACE AND ISOLATED CONVERTER CONTROLLER
Check for Samples: TPS23753
1
FEATURES
DESCRIPTION
• Optimized for Isolated Converters
• Complete PoE Interface
The TPS23753 is a combined Power over Ethernet
(PoE) powered device (PD) interface and
• Adapter ORing Support
current-mode dc/dc controller optimized specifically
• 12 V Adapter Support
for isolated converter designs. The PoE
• Programmable Frequency with Synch.
implementation supports the IEEE 802.3at standard
as a 13 W, type 1 PD. The requirements for an IEEE
• Robust 100 V, 0.7 Ω Hotswap MOSFET
802.3at type 1 device are a superset of IEEE
• Small TSSOP 14 Package
802.3-2008 (originally 802.3af) requirements.
• 15 kV / 8 kV System Level ESD Capable
The TPS23753 supports a number of input-voltage
• –40°C to 125°C Junction Temperature Range
ORing options including highest voltage, external
• Design Procedure Application Note - SLVA305
adapter preference, and PoE preference.
• Adapter ORing Application Note - SLVA306
The PoE interface features an external detection
signature pin that can also be used to disable the
APPLICATIONS
internal hotswap MOSFET. This allows the PoE
function to be turned off. Classification can be
• IEEE 802.3at Compliant Powered Devices
programmed to any of the defined types with a single
• VoIP Telephones
resistor.
• Access Points
The dc/dc controller features a bootstrap startup
• Security Cameras
mechanism with an internal, switched current source.
This provides the advantages of cycling overload fault
protection without the constant power loss of a pull up
resistor.
The programmable oscillator may be synchronized to
a higher-frequency external timing reference.
Figure 1. Basic TPS23753 Implementation
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS23753
SLVS853C –JUNE 2008–REVISED JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION
(1)
DEVICE DUTY CYCLE PoE UVLO ON / HYST. PACKAGE MARKING
TPS23753 0 – 80% 35/4.5 PW (TSSOP-14) TP23753
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Voltages are with respect to V
SS
(unless otherwise noted)
VALUE UNIT
V
DD
, V
DD1
, DEN, RTN
(2)
–0.3 to 100 V
V
DD1
to RTN –0.3 to 100 V
CLS
(3)
–0.3 to 6.5 V
V
I
Input voltage range [APD, BLNK
(3)
, CTL, FRS
(3)
, V
B
(3)
] to RTN –0.3 to 6.5 V
CS to RTN –0.3 to V
B
V
V
C
to RTN –0.3 to 19 V
GATE to RTN –0.3 to V
C
+ 0.3 V
Sourcing current V
B
Internally limited mA
Average sourcing or sinking current GATE 25 mA
RMS
HBM 2 kV
ESD rating
CDM 500 V
ESD – system level (contact/air)
(4)
8/15 kV
–40 to Internally
T
J
Operating junction temperature range °C
Limited
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) I
RTN
= 0 for V
RTN
> 80V.
(3) Do not apply voltage to these pins.
(4) Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the
TPS23753EVM-001 (HPA304-001) evaluation module (documentation available on the web). These were the test levels, not the failure
threshold.
DISSIPATION RATINGS
Ψ
JT
θ
JA
θ
JA
PACKAGE
(°C/W)
(1)
(°C/W)
(2)
(°C/W)
(1)
PW (TSSOP-14) 0.97 173.6 99.3
(1) JEDEC method with high-k board (4 layers, 2 signal and 2 planes). T
J
= T
TOP
+ (Ψ
JT
x P
J
). Use Ψ
JT
to validate T
J
from measurements.
(2) JEDEC method with low-k board (2 signal layers).
2 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com
SLVS853C –JUNE 2008–REVISED JANUARY 2010
RECOMMENDED OPERATING CONDITIONS
Voltage with respect to V
SS
(unless otherwise noted)
MIN NOM MAX UNIT
Input voltage range, V
DD
, V
DD1
, RTN 0 57 V
Input voltage range, V
DD
, V
DD1
to RTN 0 57 V
V
I
Input voltage range, V
C
to RTN 0 18 V
Input voltage range, APD, CTL to RTN 0 V
B
V
Input voltage range, CS to RTN 0 2 V
RTN current (T
J
≤ 125°C) 350 mA
V
B
sourcing current 0 2.5 5 mA
V
B
capacitance 0.08 0.1 2.2 μF
R
BLNK
0 350 kΩ
Synchronization pulse width input (when used) 25 150 ns
T
J
Operating junction temperature range –40 125 °C
ELECTRICAL CHARACTERISTICS
Unless otherwise noted: CS = APD = CTL = RTN, GATE open, R
FRS
= 60.4 kΩ, R
BLNK
= 249 kΩ, C
VB
= C
VC
= 0.1 μF,
R
DEN
= 24.9 kΩ, R
CLS
open, V
VDD-VSS
= 48 V, V
VDD1-RTN
= 48 V, 8.5 V ≤ V
VC-RTN
≤ 18 V, –40°C ≤ T
J
≤ 125°C
Controller Section Only
[V
SS
= RTN and V
DD
= V
DD1
] or [V
SS
= RTN = V
DD
], all voltages referred to RTN. Typical specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
C
UVLO
1
V
C
rising 8.65 9 9.3
Undervoltage lockout V
UVLO
H
Hysteresis
(1)
3.3 3.5 3.7
Operating current V
C
= 12 V, CTL = V
B
0.40 0.58 0.85 mA
V
DD1
= 10.2 V, V
C
(0) = 0 V 50 85 175
t
ST
Startup time, C
VC
= 22 μF ms
V
DD1
= 35 V, V
C
(0) = 0 V 30 48 85
V
DD1
= 10.2 V, V
VC
= 8.6 V 0.44 1.06 1.80
Startup current source - I
VC
mA
V
DD1
= 48 V, V
VC
= 0 V 2.5 4.3 6.0
V
B
Voltage 6.5 V ≤ V
C
≤ 18 V, 0 ≤ I
VB
≤ 5 mA 4.75 5.10 5.25 V
FRS
CTL= V
B
, Measure GATE
Switching frequency 223 248 273 kHz
R
FRS
= 60.4 kΩ
D
MAX
Duty cycle CTL= V
B
, Measure GATE 76 78.5 81 %
V
SYNC
Synchronization Input threshold 2.0 2.2 2.4 V
CTL
V
ZDC
0% duty cycle threshold V
CTL
↓ until GATE stops 1.3 1.5 1.7 V
Softstart period Interval from switching start to V
CSMAX
400 800 μs
Input resistance 70 100 145 kΩ
BLNK
In addition to t
1
Blanking delay BLNK = RTN 35 52 75 ns
R
BLNK
= 49.9 kΩ 41 52 63
(1) The hysteresis tolerance tracks the rising threshold for a given device.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS23753
TPS23753
SLVS853C –JUNE 2008–REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted: CS = APD = CTL = RTN, GATE open, R
FRS
= 60.4 kΩ, R
BLNK
= 249 kΩ, C
VB
= C
VC
= 0.1 μF,
R
DEN
= 24.9 kΩ, R
CLS
open, V
VDD-VSS
= 48 V, V
VDD1-RTN
= 48 V, 8.5 V ≤ V
VC-RTN
≤ 18 V, –40°C ≤ T
J
≤ 125°C
Controller Section Only
[V
SS
= RTN and V
DD
= V
DD1
] or [V
SS
= RTN = V
DD
], all voltages referred to RTN. Typical specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CS
V
CSMAX
Maximum threshold voltage V
CTL
= V
B
, V
CS
↑ until GATE duty cycle drops 0.50 0.55 0.60 V
t
1
Turn off delay V
CS
= 0.65 V 25 41 60 ns
V
SLOPE
Internal slope compensation voltage Peak voltage at maximum duty cycle, referred to CS 90 118 142 mV
I
SL_EX
Peak slope compensation current V
CTL
= V
B
, I
CS
at maximum duty cycle (ac component) 30 42 54 μA
Bias current (sourcing) Gate high, dc component of CS current 2 3 4.2 μA
GATE
Source current V
CTL
= V
B
, V
C
= 12 V, GATE high, Pulsed measurement 0.30 0.46 0.60 A
Sink current V
CTL
= V
B
, V
C
= 12 V, GATE low, Pulsed measurement 0.50 0.79 1.1 A
APD
V
APDEN
V
APD
↑ 1.42 1.5 1.58
Threshold voltage V
V
APDH
Hysteresis
(2)
0.28 0.3 0.32
THERMAL SHUTDOWN
Turn off temperature 135 145 155 °C
Hysteresis
(3)
20 °C
(2) The hysteresis tolerance tracks the rising threshold for a given device.
(3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
ELECTRICAL CHARACTERISTICS
PoE and Control
[V
DD
= V
DD1
] or [V
DD1
] = RTN, V
VC-RTN
= 0 V, all voltages referred to V
SS
. Typical specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEN (DETECTION) (V
DD
= V
DD1
= RTN = V
SUPPLY
positive)
Measure I
SUPPLY
Detection current V
DD
= 1.6 V 62 64.3 66.5 μA
V
DD
= 10 V 399 406 413
Detection bias current V
DD
= 10 V, DEN open, Measure I
SUPPLY
5.2 12 μA
V
PD_DIS
Hotswap disable threshold 3 4 5 V
I
lkg
DEN leakage current V
DEN
= V
DD
= 57 V, Float V
DD1
and RTN, Measure I
DEN
0.1 5 μA
CLS (CLASSIFICATION) (V
DD
= V
DD1
= RTN = V
SUPPLY
positive)
13 V ≤ V
DD
≤ 21 V, Measure I
SUPPLY
R
CLS
= 1270 Ω 1.8 2.14 2.4
R
CLS
= 243 Ω 9.9 10.6 11.3
I
CLS
Classification current mA
R
CLS
= 137 Ω 17.6 18.6 19.4
R
CLS
= 90.9 Ω 26.5 27.9 29.3
R
CLS
= 63.4 Ω 38 39.9 42
V
CL_ON
Regulator turns on, V
DD
rising 10 11.7 13
Classification regulator lower
V
threshold
V
CL_HYS
Hysteresis
(1)
1.9 2.05 2.2
V
CU_OFF
Regulator turns off, V
DD
rising 21 22 23
Classification regulator upper
V
threshold
V
CU_HYS
Hysteresis
(1)
0.5 0.77 1
I
lkg
Leakage current V
DD
= 57 V, V
CLS
= 0 V, DEN = V
SS
, Measure I
CLS
1 μA
(1) The hysteresis tolerance tracks the rising threshold for a given device.
4 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
GATE
RTN
V
C
CS
V
DD
V
SS
DEN
BLNK
FRS
V
B
CTL
CLS
1
2
3
4
5
6
7
8
14
13
11
10
9
12
APD
V
DD1
TPS23753
www.ti.com
SLVS853C –JUNE 2008–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS (continued)
PoE and Control
[V
DD
= V
DD1
] or [V
DD1
] = RTN, V
VC-RTN
= 0 V, all voltages referred to V
SS
. Typical specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RTN (PASS DEVICE) (V
DD1
= RTN)
On resistance 0.7 1.2 Ω
Current limit V
RTN
= 1.5 V, V
DD
= 48 V, Pulsed Measurement 405 450 505 mA
Inrush limit V
RTN
= 2 V, V
DD
: 0 V → 48 V, Pulsed Measurement 100 140 180 mA
Foldback voltage threshold V
DD
rising 11 12.3 13.6 V
I
lkg
Leakage current V
DD
= V
RTN
= 100 V, DEN = V
SS
40 μA
UVLO
UVLO_R V
DD
rising 33.9 35 36.1
Undervoltage lockout threshold V
UVLO_H Hysteresis
(2)
4.40 4.55 4.70
THERMAL SHUTDOWN
Turn off temperature 135 145 155 °C
Hysteresis
(3)
20 °C
(2) The hysteresis tolerance tracks the rising threshold for a given device.
(3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
DEVICE INFORMATION
TOP VIEW
Table 1. Terminal Functions
TERMINAL
I/O DESCRIPTION
NO. NAME
1 CTL I The control loop input to the PWM (pulse width modulator). Use V
B
as a pull up for CTL.
5 V bias rail for dc/dc control circuits. Apply a 0.1 μF to RTN. V
B
may be used to bias an external optocoupler for
2 V
B
O
feedback.
Dc/dc converter switching MOSFET current sense input. Connect CS to the high side of the RTN-referenced
3 CS I
current sense resistor.
Dc/dc converter bias voltage. The internal startup current source and converter bias winding output power this pin.
4 V
C
I/O
Connect a 0.22 μF minimum ceramic capacitor to RTN, and a larger capacitor to facilitate startup.
5 GATE O Gate drive output for the dc/dc converter switching MOSFET.
6 RTN RTN is the negative rail input to the dc/dc converter and output of the PoE hotswap.
7 V
SS
Negative power rail derived from the PoE source.
8 V
DD1
Source of dc/dc converter startup current. Connect to V
DD
for most applications.
9 V
DD
Positive input power rail for PoE interface circuit. Derived from the PoE source.
Connect a 24.9 kΩ resistor from DEN to V
DD
to provide the PoE detection signature. Pulling this pin to V
SS
during
10 DEN I/O
powered operation causes the internal hotswap MOSFET to turn off.
11 CLS O Connect a resistor from CLS to V
SS
to program the classification current per Table 2.
Pull APD above 1.5 V to disable the internal PD hotswap switch, forcing power to come from an external adapter.
12 APD I
Connect to the adapter through a resistor divider.
Connect to RTN to utilize the internally set blanking period or connect through a resistor to RTN to program the
13 BLNK I/O
blanking period.
14 FRS I/O Connect a resistor from FRS to RTN to program the converter switching frequency.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS23753
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