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TI-EMB1499Q.pdf
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EMB1499Q
www.ti.com
SNOSCV7B –NOVEMBER 2011–REVISED SEPTEMBER 2013
EMB1499Q Bidirectional Current DC-DC Controller
Check for Samples: EMB1499Q
1
FEATURES
DESCRIPTION
The EMB1499Q bidirectional current dc/dc controller
• 60-V Maximum Stack Operating Voltage
IC works in conjunction with the EMB1428 switch
• Bidirectional Balancing Current
matrix gate driver IC to support TI’s switch matrix
• Fully Synchronous Operation
based active cell balancing scheme for a battery
management system. The EMB1499Q provides three
• Active Clamp Signal
PWM MOSFET gate signals to a bidirectional forward
• 250-kHz Switching Frequency
converter so that its output current, either positive or
• Fault Detection Includes Two Separate UVLO
negative, is regulated around a user-defined
Cells (One for Each External Supply), Primary
magnitude. This inductor current is channeled by the
and Secondary Side Current Limit, OVP/UVP
EMB1428 through the switch matrix to the cell that
needs to be charged or discharged. In a typical
Sense on Cell Being Charged, Thermal
scheme, the EMB1499Q-based forward converter
Shutdown, and Watchdog Timer
exchanges energy between a single cell and the
• Balancing Current User-selectable Through
battery stack to which it belongs, with a maximum
External Voltage
stack voltage of up to 60 V. The switching frequency
• EMB1499Q is an Automotive Grade Product
is fixed at 250 kHz. The EMB1499Q senses cell
that is AEC-Q100 Grade 1 Qualified (–40°C to
voltage, inductor current and stack current and
provides protection from abnormal conditions during
+125°C Operating Junction Temperature)
balancing.
APPLICATIONS
The EMB1499Q also provides an active clamp timing
signal to control an external FET driver for the
• Li-Ion Battery Management Systems
primary-side active clamp FET. The EMB1499Q is
• Hybrid and Electric Vehicles
enabled and disabled by the EMB1428. Fault
• Grid Storage
conditions detected by the EMB1499Q are
communicated to the EMB1428 through the DONE
and FAULT pins.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
EMB1499
(Top View)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VINF
GNDF
N/C
GATE_HS2
PGNDF
GATE_HS1
PVINF
VINP
GNDP
GATE_LS
PWM_CLAMP
GNDA
VINA
VSENSE_LS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSENSE_HS
CELLPLUS
LOR
TM
GNDA
VSET
WDOR
EN
DIR
DONE
FAULT0
FAULT1
FAULT2
DIR_RT
FAULT2
FAULT1
FAULT0
GNDA GNDP
GNDP GND
CPU OR
MCU
EMB1428
EMB1499
Vstack
SPI BUS
DAC
MOSFET
DRIVER
DIR_RT
DONE
DIR
+12V
GNDF
PGNDF
PVINF
Floating
12V Supply
GATE_HS2
VSENSE_HS
+3.3V
VDD5V
VDDP
VDD12V
VSTACK
CEXT1
CEXT2
VDDCP
GATE[11..0]
SOURCE[11..0]
+12V
+5V
FAULT0
FAULT1
FAULT2
DONE
DIR_RT
DIR
EN
CS
SD0
SDI
SCLK
FAULT_INT
RST
7-Cell
Half-
Stack
Vstack
°
°
¯
®
VINA
VDDIO
VINF
CELLPLUS
GATE_HS1
EN
VSET
VINP
VSENSE_LS
PWM_CLAMP
GATE_LS
TO OTHER BALANCING CIRCUIT
EMB1499Q
SNOSCV7B –NOVEMBER 2011–REVISED SEPTEMBER 2013
www.ti.com
Typical Application
Figure 1. Typical Application
Connection Diagram
Figure 2. 28-Pin HTSSOP
See PWP Package
2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: EMB1499Q
EMB1499Q
www.ti.com
SNOSCV7B –NOVEMBER 2011–REVISED SEPTEMBER 2013
PIN DESCRIPTIONS
Pin Name Description Application Information
1 VSENSE_HS Secondary side current sense input Connect to transformer side of secondary sense resistor
2 CELLPLUS Senses the cell voltage, used for Connect to top of secondary side of the converter. This is the
OVP/UVP fault detection top of the cell being charged.
3 LOR Fault latch override input Grounded for normal operation.
4 TM Test mode input Grounded for normal operation.
5, 17 GNDA IC signal ground Connect to module ground at board level.
6 VSET Control voltage for adjusting the This voltage is set by the user.
balancing current
7 WDOR Watchdog timer override Grounded for normal operation.
8 EN Input from EMB1428, signals charge or Rising edge of this signal clears all fault latches, the DONE
discharge cycle to begin. latch, and initiates charge or discharge current. Falling edge of
this signal causes the charge current to ramp down to zero,
then asserts the DONE signal, causing shutdown.
9 DIR Input from EMB1428, determines the "High" indicates charge mode, "Low" indicates discharge
direction of the converter output current mode.
10 DIR_RT Output to EMB1428, inverted copy of the Used as a handshake signal to ensure DIR signal has been
DIR signal received correctly.
11 DONE Output to EMB1428, indicates that the When the EMB1499Q is disabled by toggling the EN pin low,
balancing current has ramped down the chip goes into a 'soft shutdown', ramping the charging
towards zero. current down within several hundred microseconds. When the
current has ramped down, the EMB1499Q shuts down and the
DONE signal latches high. The DONE latch is cleared at the
next rising edge of the EN signal.
12,13,14 FAULT[0,1,2] Outputs to EMB1428, three bit digital fault If a fault condition is detected, the proper three bit word is
code latched into the FAULT pins and the EMB1499Q is shut down.
The FAULT pins are cleared by the rising edge of the EN input.
15 VSENSE_LS Primary side current sense input Connect to transformer side of primary sense resistor.
16 VINA External 12V supply Powers all internal circuitry besides the primary gate side
driver. VINA and VINP should be connected together at the
board level.
18 PWM_CLAMP Output, PWM signal used to control
primary side active clamp (external driver
required)
19 GATE_LS Output, gate signal for external primary
side power FET
20 GNDP IC power ground Provides ground return for primary side gate driver. Connect to
board level ground.
21 VINP External 12V supply Powers the primary side gate driver. VINP and VINA should be
connected together at the board level.
22 PVINF External floating 12V supply This floating supply must be referenced to the bottom of the
transformer secondary. Supplies power to the secondary side
gate drivers. PVINF and VINF should be connected together at
the board level.
23 GATE_HS1 Output, gate signal for external secondary
side power FET
24 PGNDF Floating power ground Connect to secondary side of converter. Provides the ground
return for the secondary side gate drivers.
25 GATE_HS2 Output, gate signal for external secondary
side power FET
26 N/C No connect No connect pin. Do not connect
27 GNDF Floating signal ground Connected to secondary side of converter. Provides ground
reference for all internal circuitry that floats with the transformer
secondary except the secondary side gate drivers.
28 VINF External floating 12V supply This floating supply must be referenced to the bottom of the
transformer secondary. Supplies power to all internal circuitry
that floats with the transformer secondary except the
secondary side gate drivers. PVINF and VINF should be
connected together at the board level.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: EMB1499Q
EMB1499Q
SNOSCV7B –NOVEMBER 2011–REVISED SEPTEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1)
VINA, VINP to GND -0.5V to 15V
VINF, PVINF to GNDF -0.5V to 15V
GNDF to GND -0.5V to 60V
VSENSE_LS to GND -0.5V to 0.5V
VSENSE_HS to GNDF -0.5V to 0.5V
VSET to GND -0.5V to 7.5V
CELLPLUS to GNDF -0.5V to 7.5V
All other inputs to GND -0.5V to 15V
ESD Rating
(2)
Human Body Model ±2kV
Soldering Information Junction Temperature 150°C
Storage Temperature -65°C to 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/ or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings
indicate conditions at which the device is functional and should not be operated beyond such conditions.
(2) The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22 –A114.
OPERATING RATINGS
VINA, VINP to GND 10V to 14V
VINF, PVINF to GNDF 10V to 14V
GNDF to GND 0V to 56V
VSENSE_LS to GND -0.2V to 0.2V
VSENSE_HS to GNDF -0.2V to 0.2V
VSET to GND 1V to 2.2V
CELLPLUS to GNDF 0V to 6V
All other inputs to GND 0V to 14V
Junction Temperature (T
J
) -40°C to 125°C
4 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: EMB1499Q
EMB1499Q
www.ti.com
SNOSCV7B –NOVEMBER 2011–REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of −40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. For all tests, VINA = VINP =
VINF = PVINF = 12V unless otherwise specified.
Symbol Parameter Conditions Min Typ
(1)
Max Units
Feedback Voltage
V
SENSE_HS
Feedback Voltage VSET = 2V 45 50 55 mV
VSET = 1.2V 24 30 36 mV
Switching Parameters
F
SW
Switching Frequency 220 250 290 kHz
D
MAX
Maximum Duty Cycle Charge 91 %
Direction
Discharge 91 %
Direction
D
MIN
Minimum Duty Cycle Charge 4 %
Direction
Discharge 3 %
Direction
Operating Thresholds
UVLO Under-voltage Lockout VINA, VINP, 10.8 V
VINF, PVINF
Rising
VINA, VINP, 5 V
VINF, PVINF
Falling
V
EN_TH
Enable Threshold EN Rising 1.55 V
EN Falling 0.45 V
V
DIR_TH
Direction Threshold DIR Rising 2.75 V
DIR Falling 2.2 V
Quiescent Currents
I
Q_VINA
VINA Quiescent Current VSET = 2V, 2 2.8 mA
(Operating) VSENSE_HS =
0V
VINA Quiescent Current EN = 0V <1 2.3 µA
(Shutdown)
I
Q_VINP
VINP Quiescent Current VEN = 0V <1 2.3 µA
(Shutdown)
I
Q_VINF
VINF Quiescent Current VSET = 2V, 1.5 1.9 mA
(Operating) VSENSE_HS =
0V
VINF Quiescent Current EN = 0V <1 2 µA
(Shutdown)
I
Q_PVINF
VPINF Quiescent Current EN = 0V <1 2.5 µA
(Shutdown)
I
Q_CELLPLUS
CELLPLUS Quiescent Current VSET = 2V, 18 30 µA
(Operating) VSENSE_HS =
0V
Fault Detection
V
CL_LS
Primary Side Current Limit 100 132 170 mV
V
CL_HS
Secondary Side Current Limit 95 136 185 mV
V
OVP
Cell OVP Threshold Voltage CELLPLUS 4.5 5.5 7 V
Rising
CELLPLUS 5 V
Falling
(1) Typical specifications represent the most likely parametric norm at 25°C operation.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: EMB1499Q
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