core-fsl-emb.rar_.emb_Core Performance

/* Freescale Embedded Performance Monitor */ #include <linux/kernel.h> #include <linux/sched.h> #include <linux/perf_event.h> #include <linux/percpu.h> #include <linux/hardirq.h> #include <asm/reg_fsl_emb.h> #include <asm/pmc.h> #include <asm/machdep.h> #include <asm/firmware.h> #include <asm/ptrace.h> struct cpu_hw_events { int n_events; int disabled; u8 pmcs_enabled; struct perf_event *event[MAX_HWEVENTS]; }; static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); static struct fsl_emb_pmu *ppmu; /* Number of perf_events counting hardware events */ static atomic_t num_events; /* Used to avoid races in calling reserve/release_pmc_hardware */ static DEFINE_MUTEX(pmc_reserve_mutex); /* * If interrupts were soft-disabled when a PMU interrupt occurs, treat * it as an NMI. */ static inline int perf_intr_is_nmi(struct pt_regs *regs) { #ifdef __powerpc64__ return !regs->softe; #else return 0; #endif } static void perf_event_interrupt(struct pt_regs *regs); /* * Read one performance monitor counter (PMC). */ static unsigned long read_pmc(int idx) { unsigned long val; switch (idx) { case 0: val = mfpmr(PMRN_PMC0); break; case 1: val = mfpmr(PMRN_PMC1); break; case 2: val = mfpmr(PMRN_PMC2); break; case 3: val = mfpmr(PMRN_PMC3); break; case 4: val = mfpmr(PMRN_PMC4); break; case 5: val = mfpmr(PMRN_PMC5); break; default: printk(KERN_ERR "oops trying to read PMC%d\n", idx); val = 0; } return val; } /* * Write one PMC. */ static void write_pmc(int idx, unsigned long val) { switch (idx) { case 0: mtpmr(PMRN_PMC0, val); break; case 1: mtpmr(PMRN_PMC1, val); break; case 2: mtpmr(PMRN_PMC2, val); break; case 3: mtpmr(PMRN_PMC3, val); break; case 4: mtpmr(PMRN_PMC4, val); break; case 5: mtpmr(PMRN_PMC5, val); break; default: printk(KERN_ERR "oops trying to write PMC%d\n", idx); } isync(); } /* * Write one local control A register */ static void write_pmlca(int idx, unsigned long val) { switch (idx) { case 0: mtpmr(PMRN_PMLCA0, val); break; case 1: mtpmr(PMRN_PMLCA1, val); break; case 2: mtpmr(PMRN_PMLCA2, val); break; case 3: mtpmr(PMRN_PMLCA3, val); break; case 4: mtpmr(PMRN_PMLCA4, val); break; case 5: mtpmr(PMRN_PMLCA5, val); break; default: printk(KERN_ERR "oops trying to write PMLCA%d\n", idx); } isync(); } /* * Write one local control B register */ static void write_pmlcb(int idx, unsigned long val) { switch (idx) { case 0: mtpmr(PMRN_PMLCB0, val); break; case 1: mtpmr(PMRN_PMLCB1, val); break; case 2: mtpmr(PMRN_PMLCB2, val); break; case 3: mtpmr(PMRN_PMLCB3, val); break; case 4: mtpmr(PMRN_PMLCB4, val); break; case 5: mtpmr(PMRN_PMLCB5, val); break; default: printk(KERN_ERR "oops trying to write PMLCB%d\n", idx); } isync(); } static void fsl_emb_pmu_read(struct perf_event *event) { s64 val, delta, prev; if (event->hw.state & PERF_HES_STOPPED) return; /* * Performance monitor interrupts come even when interrupts * are soft-disabled, as long as interrupts are hard-enabled. * Therefore we treat them like NMIs. */ do { prev = local64_read(&event->hw.prev_count); barrier(); val = read_pmc(event->hw.idx); } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); /* The counters are only 32 bits wide */ delta = (val - prev) & 0xfffffffful; local64_add(delta, &event->count); local64_sub(delta, &event->hw.period_left); } /* * Disable all events to prevent PMU interrupts and to allow * events to be added or removed. */ static void fsl_emb_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuhw; unsigned long flags; local_irq_save(flags); cpuhw = &__get_cpu_var(cpu_hw_events); if (!cpuhw->disabled) { cpuhw->disabled = 1; /* * Check if we ever enabled the PMU on this cpu. */ if (!cpuhw->pmcs_enabled) { ppc_enable_pmcs(); cpuhw->pmcs_enabled = 1; } if (atomic_read(&num_events)) { /* * Set the 'freeze all counters' bit, and disable * interrupts. The barrier is to make sure the * mtpmr has been executed and the PMU has frozen * the events before we return. */ mtpmr(PMRN_PMGC0, PMGC0_FAC); isync(); } } local_irq_restore(flags); } /* * Re-enable all events if disable == 0. * If we were previously disabled and events were added, then * put the new config on the PMU. */ static void fsl_emb_pmu_enable(struct pmu *pmu) { struct cpu_hw_events *cpuhw; unsigned long flags; local_irq_save(flags); cpuhw = &__get_cpu_var(cpu_hw_events); if (!cpuhw->disabled) goto out; cpuhw->disabled = 0; ppc_set_pmu_inuse(cpuhw->n_events != 0); if (cpuhw->n_events > 0) { mtpmr(PMRN_PMGC0, PMGC0_PMIE | PMGC0_FCECE); isync(); } out: local_irq_restore(flags); } static int collect_events(struct perf_event *group, int max_count, struct perf_event *ctrs[]) { int n = 0; struct perf_event *event; if (!is_software_event(group)) { if (n >= max_count) return -1; ctrs[n] = group; n++; } list_for_each_entry(event, &group->sibling_list, group_entry) { if (!is_software_event(event) && event->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) return -1; ctrs[n] = event; n++; } } return n; } /* context locked on entry */ static int fsl_emb_pmu_add(struct perf_event *event, int flags) { struct cpu_hw_events *cpuhw; int ret = -EAGAIN; int num_counters = ppmu->n_counter; u64 val; int i; perf_pmu_disable(event->pmu); cpuhw = &get_cpu_var(cpu_hw_events); if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) num_counters = ppmu->n_restricted; /* * Allocate counters from top-down, so that restricted-capable * counters are kept free as long as possible. */ for (i = num_counters - 1; i >= 0; i--) { if (cpuhw->event[i]) continue; break; } if (i < 0) goto out; event->hw.idx = i; cpuhw->event[i] = event; ++cpuhw->n_events; val = 0; if (event->hw.sample_period) { s64 left = local64_read(&event->hw.period_left); if (left < 0x80000000L) val = 0x80000000L - left; } local64_set(&event->hw.prev_count, val); if (!(flags & PERF_EF_START)) { event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; val = 0; } write_pmc(i, val); perf_event_update_userpage(event); write_pmlcb(i, event->hw.config >> 32); write_pmlca(i, event->hw.config_base); ret = 0; out: put_cpu_var(cpu_hw_events); perf_pmu_enable(event->pmu); return ret; } /* context locked on entry */ static void fsl_emb_pmu_del(struct perf_event *event, int flags) { struct cpu_hw_events *cpuhw; int i = event->hw.idx; perf_pmu_disable(event->pmu); if (i < 0) goto out; fsl_emb_pmu_read(event); cpuhw = &get_cpu_var(cpu_hw_events); WARN_ON(event != cpuhw->event[event->hw.idx]); write_pmlca(i, 0); write_pmlcb(i, 0); write_pmc(i, 0); cpuhw->event[i] = NULL; event->hw.idx = -1; /* * TODO: if at least one restricted event exists, and we * just freed up a non-restricted-capable counter, and * there is a restricted-capable counter occupied by * a non-restricted event, migrate that event to the * vacated counter. */ cpuhw->n_events--; out: perf_pmu_enable(event->pmu); put_cpu_var(cpu_hw_events); } static void fsl_emb_pmu_start(struct perf_event *event, int ef_flags) { unsigned long flags; s64 left; if (event->hw.idx < 0 || !event->hw.sample_period) return; if (!(event->hw.state & PERF_HES_STOPPED)) return; if (ef_flags & PERF_EF_RELOAD) WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); local_irq_save(flags); perf_pmu_disable(event->pmu); event->hw.state = 0; left = local64_read(&event->hw.period_left); write_pmc(event->hw.idx, left); perf_event_update_userpage(event); perf_pmu_enable(event->pmu); local_irq_restore(flags); } static void fsl_emb_pmu_stop(struct perf_event *event, int ef_flags) { unsigned long flags; if (event->hw.idx < 0 || !event->hw.sample_period) return; if (event->hw.sta