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TI-UCC24624.pdf TI-UCC24624 是一款高性能同步整流器（SR）控制器，专门用于 LLC 谐振转换器，以使用 SR MOSFET 替代有损耗二极管输出整流器并提高整体系统效率。该控制器使用漏源极电压检测方法来实现 SR MOSFET 的开关控制，并实现了比例栅极驱动器，以延长 SR 导通时间并最大程度地缩短体二极管导通时间。 UCC24624 具有多种特性，包括： 1.230V VD 引脚额定值 2.23ns 关断延迟，支持 LLC 以高于谐振频率和高达 625kHz 的开关频率运行 3.比例栅极驱动器，可延长 SR 导通时间 4.可调节关断阈值，可最大程度地减小体二极管导通时间 5.具有 180µA 低待机电流的自动待机模式检测 6.具有内部钳位的 4.25V 至 26V 宽 VDD 工作范围 7.自适应导通延迟，可实现更佳的 DCM 振铃抑制 8.双通道互锁，可防止击穿 UCC24624 的应用场景包括： 1.台式计算机、一体式计算机、ATX 和服务器电源 2.交流/直流适配器 3.LCD、LED 和 OLED 电视 4.工业交流/直流和隔离式直流/直流电源 5.电动工具充电器、LED 照明电源在使用 UCC24624 时，可以借助 WEBENCH® 电源设计器创建定制设计，快速实现高效的电源解决方案。 UCC24624 的 Pin 配置和功能： 1.VG1：输入电压引脚 2.PGND：电源地引脚 3.REGVD1：输入电压调整引脚 4.VSS：电源地引脚 5.VD2：输出电压检测引脚 6.VDD：电源电压引脚 7.UCC24624：控制器芯片 8.Q1、Q2：SR MOSFET 输出管脚 9.Lr、Cr：输出电感和电容引脚 10.Vin、Vout：输入和输出电压引脚 11.S1、S2：同步信号引脚 UCC24624 的规格包括： 1.Absolute Maximum Ratings：包括最高电压、电流和温度等参数 2.Electrical Characteristics：包括输入电压、输出电压、电流等参数 3.Timing Characteristics：包括开关频率、关断延迟等参数 UCC24624 是一款高性能的同步整流器控制器，适合用于 LLC 谐振转换器，能够提高整体系统效率和可靠性。

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本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSD48

UCC24624

ZHCSIL2B –JULY 2018–REVISED NOVEMBER 2018

适适用用于于 LLC 谐谐振振转转换换器器的的 UCC24624 双双通通道道同同步步整整流流器器控控制制器器

1 特特性性

• 230V VD 引脚额定值

• 23ns 关断延迟，支持 LLC 以高于谐振频率和高达

625kHz 的开关频率运行

• 比例栅极驱动器，可延长 SR 导通时间

• 可调节关断阈值，可最大程度地减小体二极管导通

时间

• 具有 180µA 低待机电流的自动待机模式检测

• 具有内部钳位的 4.25V 至 26V 宽 VDD 工作范围

• 自适应导通延迟，可实现更佳的 DCM 振铃抑制

• 双通道互锁，可防止击穿

• 适用于 N 沟道 MOSFET 的集成式 1.5A 拉电流和

4A 灌电流能力栅极驱动器

• 8 管脚 SOIC 封装

2 应应用用

• 台式计算机、一体式计算机、ATX 和服务器电源

• 交流/直流适配器

• LCD、LED 和 OLED 电视

• 工业交流/直流和隔离式直流/直流电源

• 电动工具充电器、LED 照明电源

• 使用 UCC24624 并借助 WEBENCH

电源设计器

创建定制设计

3 说说明明

UCC24624 高性能同步整流器 (SR) 控制器专用于

LLC 谐振转换器，以使用 SR MOSFET 替代有损耗二

极管输出整流器并提高整体系统效率。

UCC24624 SR 控制器使用漏源极电压检测方法来实现

SR MOSFET 的开关控制。实现了比例栅极驱动器，

以延长 SR 导通时间并最大程度地缩短体二极管导通时

间。为了补偿由 SR MOSFET 寄生电感导致的偏移电

压，UCC24624 实现了可调节正向关断阈值，以适应

不同的 SR MOSFET 封装。UCC24624 具有内置的

475ns 导通时间消隐和固定的 650ns 关断时间消隐功

能，以避免 SR 错误导通和关断。UCC24624 还集成

了双通道互锁功能，可防止两个 SR 同时导通。该器件

具有 230V 电压检测引脚和 28V 绝对最大 VDD 额定

值，可直接用于输出电压高达 24.75V 的转换器。内部

钳位允许控制器通过在 VDD 上添加外部电流限制电阻

器来轻松支持 36V 输出电压。

器器件件信信息息

(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

UCC24624 SOIC (8) 4.90mm × 3.91mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

空白

典典型型应应用用原原理理图图

UCC24624

ZHCSIL2B –JULY 2018–REVISED NOVEMBER 2018

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 说说明明（（续续））............................................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements................................................ 7

7.7 Typical Characteristics.............................................. 8

8 Detailed Description............................................ 10

8.1 Overview ................................................................. 10

8.2 Functional Block Diagram ....................................... 11

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 20

9 Application and Implementation ........................ 21

9.1 Application Information............................................ 21

9.2 Typical Application ................................................. 21

10 Power Supply Recommendations ..................... 25

11 Layout................................................................... 26

11.1 Layout Guidelines ................................................. 26

11.2 Layout Example .................................................... 26

12 器器件件和和文文档档支支持持 ..................................................... 28

12.1 器件支持 ............................................................... 28

12.2 接收文档更新通知 ................................................. 28

12.3 社区资源................................................................ 28

12.4 商标 ....................................................................... 28

12.5 静电放电警告......................................................... 28

12.6 术语表 ................................................................... 28

13 机机械械、、封封装装和和可可订订购购信信息息....................................... 29

4 修修订订历历史史记记录录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (September 2018) to Revision B Page

• 首次发布生产数据数据表 ........................................................................................................................................................ 1

PGND

REG

VG2

VSS

VG1

VD1

VD2

VDD

UCC24624

ZHCSIL2B –JULY 2018–REVISED NOVEMBER 2018

www.ti.com.cn

6 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

Pin Functions

I/O DESCRIPTION

NO. NAME

1 VG1 O

VG1 is the controlled MOSFET gate drive for channel 1. Connect VG1 to the gate of the channel 1

SR MOSFET through a small series resistor using short PCB traces to achieve optimal switching

performance. The VG1 output can achieve 1.5-A peak source current, and 4-A peak sink current

when connected to a large N-channel power MOSFET.

2 PGND -

PGND is the power return pin of the UCC24624. The IC bias current and high peak current from the

gate drivers return to this pin. Short PCB traces and the ceramic bypass capacitor are required to

minimize the high slew rate current impacts to the IC operation. The PGND should be connected

directly to the SR MOSFET source pins.

3 REG O

REG is the internal linear regulator output and the device's internal bias pin. An internal linear

regulator from VDD to REG generates a well-regulated 11-V voltage. TI recommends putting a 2.2-μF

bypass capacitor from REG pin to PGND pin.

4 VD1 I

VD1 is the channel 1 SR MOSFET drain voltage sensing input. Connect this pin to channel 1 SR

MOSFET drain pin. The layout should avoid the VD1 pin trace sharing the power path to minimize the

impacts of parasitic inductance.

5 VSS I

VSS is used to sense the voltage drop across the SR MOSFETs. Since both channels are sharing

the same VSS pin to sense the MOSFET voltage, special attention is required. The layout should

avoid the VSS pin trace sharing the power path to minimize the impacts of parasitic inductor. See

Layout Example for more details. A resistor can be added between VSS pin and SR MOSFET source

pins to adjust the SR turn-off threshold if it is needed.

6 VD2 I

VD2 is the channel 2 SR MOSFET drain voltage sensing input. Connect this pin to channel 2 SR

MOSFET drain pin. The layout must avoid the VD2 pin trace sharing the power path to minimize the

impacts of parasitic inductance.

7 VDD I

VDD is the internal linear regulator input. Connect this pin to the output voltage when the output

voltage is less than 24.75 V. When the output voltage is higher than 24.75 V, add a series resistor

between LLC output voltage and the VDD pin to limit the internal clamping circuit current.

8 VG2 O

VG2 is the controlled MOSFET gate drive for channel 2. Connect VG2 to the gate of the channel 2

MOSFET through a small series resistor using short PCB traces to achieve optimal switching

performance. The VG2 output can achieve 1.5-A peak source current and 4-A peak sink current

when connected to a large N-channel power MOSFET.

UCC24624

www.ti.com.cn

ZHCSIL2B –JULY 2018–REVISED NOVEMBER 2018

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) VDD is internally clamped at 27.5 V typical with 15 mA of sink current capability.

(3) In normal use, VG1 or VG2 is connected to the gate of a power MOSFET through a small resistor. When used this way, VG1 or

VG2current is limited by the UCC24624 and no absolute maximum output current considerations are required. The series resistor shall

beselected to minimize overshoot and ringing due to series inductance of the VG1 or VG2 output and power-MOSFET gate-drive

loop.Continuous VG1 or VG2 current is subject to the maximum operating junction temperature limitation.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN MAX UNIT

Input voltage

(1)

VDD

(2)

–0.3 28 V

VD1, VD2 –0.7 230 V

VD1, VD2 for I

VD1

, I

VD2

≤ –10 mA and less than 300 ns –2 230 V

Output voltage

VG1, VG2 –0.3 V

REG

+0.7 V

REG 13.5 V

Output current,

peak

VG1 or VG2

(3)

pulsed, t

PULSE

≤ 4 ms, duty cycle ≤ 1% ±4 A

Junction temperature –40 125 °C

stg

Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001

(1)

All pins except pins 4 and 6 ±2000 V

Pins 4 and 6 ±1000 V

Charged device model (CDM), per

JEDEC specificationJESD22-

C101

(2)

All pins ±500 V

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VDD

Supply voltage 4.25 26 V

VDD

VDD bypass capacitor 0.1 µF

REG

REG pin bypass capacitor 2.2 µF

VD1

, V

VD2

Voltage on sensing pins –0.5 200 V

Switching frequency 625 kHz

Junction temperature -40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC

(1)

DEVICE

UNITD (SOIC)

8 PINS

θJA

Junction-to-ambient thermal resistance 108.4 °C/W

θJC(top)

Junction-to-case (top) thermal resistance 43.5 °C/W

θJB

Junction-to-board thermal resistance 53.6 °C/W

Junction-to-top characterization parameter 4.9 °C/W

剩余37页未读，继续阅读

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