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PCI Express Base Specification Revision 4.0 Version 0.7
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PCI Express
®
Base Specification
Revision 4.0 Version 0.7
February, 2016
2
Revision Revision History DATE
1.0
Initial release.
07/22/2002
1.0a
Incorporated Errata C1-C66 and E1-E4.17.
04/15/2003
1.1
Incorporated approved Errata and ECNs.
03/28/2005
2.0 Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. 12/20/2006
2.1 Incorporated Errata for the PCI Express Base Specification, Rev. 2.0
(February 27, 2009), and added the following ECNs:
• Internal Error Reporting ECN (April 24, 2008)
• Multicast ECN (December 14, 2007, approved by PWG May 8, 2008)
• Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008)
• Resizable BAR Capability ECN (January 22, 2008, updated and approved by
PWG April 24, 2008)
• Dynamic Power Allocation ECN (May 24, 2008)
• ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008)
• Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008)
• Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated
June 4, 2007)
• Extended Tag Enable Default ECN (September 5, 2008)
• TLP Processing Hints ECN (September 11, 2008)
•
TLP Prefix ECN (December 15, 2008)
03/04/2009
3.0
Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs:
• Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009)
• ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009)
• Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol
Multiplexing ECN (17 June 2010)
11/10/2010
3.1 Incorporated feedback from Member Review
Incorporated Errata for the PCI Express® Base Specification Revision 3.0
Incorporated M-PCIe Errata (3p1_active_errata_list_mpcie_28Aug2014.doc and
3p1_active_errata_list_mpcie_part2_11Sept2014.doc)
Incorporated the following ECNs:
• ECN: Downstream Port containment (DPC)
• ECN: Separate Refclk Independent SSC (SRIS) Architecture
• ECN: Process Address Space ID (PASID)
• ECN: Lightweight Notification (LN) Protocol
• ECN: Precision Time Measurement
• ECN: Enhanced DPC (eDPC)
• ECN: 8.0 GT/s Receiver Impedance
• ECN: L1 PM Substates with CLKREQ
• ECN: Change Root Complex Event Collector Class Code
• ECN: M-PCIe
• ECN: Readiness Notifications (RN)
• ECN: Separate Refclk Independent SSC Architecture (SRIS) JTOL and SSC
Profile Requirements
10/8/2014
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
3
4.0 Version 0.3: Based on PCI Express® Base Specification Revision 3.1
(October 8, 2014) with some editorial feedback received in December 2013.
• Added Chapter 9, Electrical Sub-block: Added Chapter 9 (Rev0.3-11-30-
13_final.docx)
• Changes related to Revision 0.3 release
• Incorporated PCIe-relevant material from PCI Bus Power Management Interface
Specification (Revision 1.2, dated March 3, 2004). This initial integration of the
material will be updated as necessary and will supercede the standalone Power
Management Interface specification.
Version 0.5 (12/22/14, minor revisions on 1/26/15, minor corrections 2/6/15)
• Added front matter with notes on expected discussions and changes.
• Added ECN:Retimer (dated October 6, 2014)
• Corrected Chapter 4 title to, “Physical Layer Logical Block”.
• Added Encoding subteam feedback on Chapter 4
• Added Electrical work group changes from PCIe Electrical Specification Rev 0.5
RC1 into Chapter 9
Version 0.7: Based on PCI Express® Base Specification Version 4.0 Revision 0.5
(11/23/2015)
• Added ECN_DVSEC-2015-08-04
• Applied ECN PASID-ATS dated 2011-03-31
• Applied PCIE Base Spec Errata: PCIe_Base_r3 1_Errata_2015-09-18
except:
o B216; RCIE
o B256; grammar is not clear
• Changes to Chapter 7. Software Initialization and Configuration per
PCIe_4.0_regs_0-3F_gord_7.docx
• Added Chapter SR-IOV Spec Rev 1.2
(Rev 1.1 dated September 8, 2009 plus:
o SR-IOV_11_errata_table.doc
o DVSEC
o 3.1 Base Spec errata)
• Added Chapter ATS Spec Rev 1.2
(Rev 1.1 dated January 26, 2009 plus:
o ECN-PASID-ATS
o 3.1 Base Spec errata)
2/18/2016 Changes from the Protocol Working Group
• Applied changes from the following documents:
o FC Init/Revision | scaled-flow-control-pcie-base40-2016-01-
07.pdf (Steve.G)
o Register updates for integrated legacy specs | PCIe_4.0_regs_0-
3F_gord_8.docx (GordC)
o Tag Scaling PCIe 4_0 Tag Field scaling 2015-11-23 clean.docx
(JoeC)
o MSI/MSI-X | PCIe 4_0 MSI & MSI-X 2015-12-18 clean.docx
(JoeC); register diagrams TBD on next draft.
o REPLAY_TIMER/Ack/FC Limits | Ack_FC_Replay_Timers_ver8
(PeterJ)
2/6/2015
11/24/2015
2/18/16
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
4
PCI-SIG
®
disclaims all warranties and liability for the use of this document and the information contained herein and
assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to
update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of this specification.
Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to:
Membership Services
www.pcisig.com
E-mail: administration@pcisig.com
Phone: 503-619-0569
Fax: 503-644-6708
Technical Support
techsupp@pcisig.com
DISCLAIMER
This PCI Express Base Specification is provided “as is” with no warranties whatsoever, including any warranty of
merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any
proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to
use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted herein.
PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.
All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
Copyright © 2002-2016 PCI-SIG
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
5
Contents
OBJECTIVE OF THE SPECIFICATION ............................................................................... 43
DOCUMENT ORGANIZATION.............................................................................................. 43
DOCUMENTATION CONVENTIONS ................................................................................... 43
TERMS AND ACRONYMS ...................................................................................................... 44
REFERENCE DOCUMENTS ................................................................................................... 55
1 INTRODUCTION............................................................................................................... 56
1.1 A THIRD GENERATION I/O INTERCONNECT ................................................................... 56
1.2 PCI EXPRESS LINK ......................................................................................................... 59
1.3 PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 60
1.3.1 Root Complex ............................................................................................................ 60
1.3.2 Endpoints .................................................................................................................. 61
1.3.3 Switch ........................................................................................................................ 64
1.3.4 Root Complex Event Collector .................................................................................. 65
1.3.5 PCI Express to PCI/PCI-X Bridge ............................................................................ 65
1.4 PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 65
1.5 PCI EXPRESS LAYERING OVERVIEW .............................................................................. 66
1.5.1 Transaction Layer ..................................................................................................... 67
1.5.2 Data Link Layer ........................................................................................................ 67
1.5.3 Physical Layer .......................................................................................................... 68
1.5.4 Layer Functions and Services ................................................................................... 68
2 TRANSACTION LAYER SPECIFICATION ................................................................. 72
2.1 TRANSACTION LAYER OVERVIEW.................................................................................. 72
2.1.1 Address Spaces, Transaction Types, and Usage ....................................................... 73
2.1.2 Packet Format Overview .......................................................................................... 75
2.2 TRANSACTION LAYER PROTOCOL - PACKET DEFINITION ............................................... 77
2.2.1 Common Packet Header Fields ................................................................................ 77
2.2.2 TLPs with Data Payloads - Rules ............................................................................. 80
2.2.3 TLP Digest Rules ...................................................................................................... 84
2.2.4 Routing and Addressing Rules .................................................................................. 84
2.2.5 First/Last DW Byte Enables Rules ............................................................................ 88
2.2.6 Transaction Descriptor ............................................................................................. 91
2.2.7 Memory, I/O, and Configuration Request Rules ..................................................... 101
2.2.8 Message Request Rules ........................................................................................... 109
2.2.9 Completion Rules .................................................................................................... 130
2.2.10 TLP Prefix Rules ................................................................................................. 134
2.3 HANDLING OF RECEIVED TLPS .................................................................................... 139
2.3.1 Request Handling Rules .......................................................................................... 142
2.3.2 Completion Handling Rules .................................................................................... 154
2.4 TRANSACTION ORDERING ............................................................................................ 158
2.4.1 Transaction Ordering Rules ................................................................................... 158
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