PCI Express
Card Electromechanical Specification
Revision 4.0, Version 0.9 4
4.7. Electrical Budgets ....................................................................................................... 48
4.7.1. AC Coupling Capacitors .................................................................................................. 48
4.7.2. Insertion Loss Values (Voltage Transfer Function) ......................................................... 48
4.7.3. Jitter Values 48
4.7.4. Crosstalk 51
4.7.5. Lane-to-Lane Skew ......................................................................................................... 51
4.7.6. Transmitter Equalization .................................................................................................. 52
4.7.7. Skew within the Differential Pair ...................................................................................... 52
4.7.8. Differential Data Trace Impedance.................................................................................. 52
4.7.9. Differential Data Trace Propagation Delay ...................................................................... 53
4.7.10. Add-in Card Insertion Loss Limit for 16.0 GT/s ............................................................... 53
4.8. Eye Diagrams at the Add-in Card Interface ................................................................ 53
4.8.1. Add-in Card Transmitter Path Compliance Eye Diagram at 2.5 GT/s ............................. 54
4.8.2. Add-in Card Transmitter Path Compliance Eye Diagrams at 5.0 GT/s ........................... 55
4.8.3. Add-in Card Transmitter Path Compliance Eye Diagrams at 8.0 GT/s ........................... 57
4.8.4. Add-in Card Transmitter Path Compliance Eye Diagrams at 16.0 GT/s ......................... 57
4.8.5. Add-in Card Transmitter Path Pulse Width Jitter at 16.0 GT/s ....................................... 58
4.8.6. Add-in Card Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s .................. 59
4.8.7. Add-in Card Minimum Receiver Path Sensitivity Requirements at 5.0 GT/s .................. 60
4.8.8. Add-in Card Minimum Receiver Path Sensitivity Requirements at 8.0 GT/s .................. 61
4.8.9. Add-in Card Minimum Receiver Path Sensitivity Requirements at 16.0 GT/s ................ 62
4.8.10. System Board Transmitter Path Compliance Eye Diagram at 2.5 GT/s ......................... 64
4.8.11. System Board Transmitter Path Compliance Eye Diagram at 5.0 GT/s ......................... 65
4.8.12. System Board Transmitter Path Compliance Eye Diagram at 8.0 GT/s ......................... 68
4.8.13. System Board Transmitter Path Compliance Eye Diagram at 16.0 GT/s ....................... 71
4.8.14. System Board Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s ............... 73
4.8.15. System Board Minimum Receiver Path Sensitivity Requirements at 5.0 GT/s ............... 74
4.8.16. System Board Minimum Receiver Path Sensitivity Requirements at 8.0 GT/s ............... 76
4.8.17. System Board Minimum Receiver Path Sensitivity Requirements at 16.0 GT/s ............. 77
5. 150 W, 225 W, AND 300 W ADD-IN CARD POWER .......................................................... 78
5.1. 150 W Add-in Card Power-Up Sequencing ................................................................. 80
5.2. 225 W and 300 W Add-in Card Power-Up Sequencing ............................................... 82
6. CARD CONNECTOR SPECIFICATION .............................................................................. 86
6.1. Connector Pinout ........................................................................................................ 86
6.2. Connector Interface Definitions .................................................................................. 89
6.3. Signal Integrity Requirements and Test Procedures ................................................... 95
6.3.1. Signal Integrity Requirements ......................................................................................... 95
6.3.2. Signal Integrity Requirements and Test Procedures for 2.5 GT/s Support ..................... 95
6.3.3. Signal Integrity Requirements and Test Procedures for 5.0 GT/s Support ..................... 98
6.3.3.1 Test Fixture Requirements .................................................................... 100
6.3.4. Signal Integrity Requirements and Test Procedures for 8.0 GT/s Support ................... 100
6.3.4.1 Test Fixture Requirements .................................................................... 102
6.3.5. Signal Integrity Requirements and Test Procedures for 16.0 GT/s Support ................. 102
6.3.6. Test Fixture Requirements ............................................................................................ 105
6.4. Connector Environmental and Other Requirements.................................................. 108
6.4.1. Environmental Requirements ........................................................................................ 108
6.4.2. Mechanical Requirements ............................................................................................. 110
6.4.3. Current Rating Requirement ......................................................................................... 110
6.4.4. Additional Considerations .............................................................................................. 111
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