PCI Express Card Electromechanical Specification
PCI Express Card Electromechanical Specification
Revision 4.0, Version 1.0 4
4.7. Electrical Budgets ....................................................................................................... 49
4.7.1. AC Coupling Capacitors .................................................................................................. 49
4.7.2. Insertion Loss Values (Voltage Transfer Function) ......................................................... 49
4.7.3. Jitter Values ................................................................................................................ 49
4.7.4. Crosstalk ................................................................................................................ 52
4.7.5. Lane-to-Lane Skew ......................................................................................................... 52
4.7.6. Transmitter Equalization .................................................................................................. 53
4.7.7. Skew within the Differential Pair ...................................................................................... 53
4.7.8. Differential Data Trace Impedance.................................................................................. 53
4.7.9. Differential Data Trace Propagation Delay ...................................................................... 54
4.7.10. Add-in Card Insertion Loss Limit for 16.0 GT/s ............................................................... 54
4.8. Eye Diagrams at the Add-in Card Interface ................................................................ 54
4.8.1. Add-in Card Transmitter Path Compliance Eye Diagram at 2.5 GT/s ............................. 55
4.8.2. Add-in Card Transmitter Path Compliance Eye Diagrams at 5.0 GT/s ........................... 56
4.8.3. Add-in Card Transmitter Path Compliance Eye Diagrams at 8.0 GT/s ........................... 58
4.8.4. Add-in Card Transmitter Path Compliance Eye Diagrams at 16.0 GT/s ......................... 58
4.8.5. Add-in Card Transmitter Path Pulse Width Jitter at 16.0 GT/s ....................................... 59
4.8.6. Add-in Card Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s .................. 60
4.8.7. Add-in Card Minimum Receiver Path Sensitivity Requirements at 5.0 GT/s .................. 61
4.8.8. Add-in Card Minimum Receiver Path Sensitivity Requirements at 8.0 GT/s .................. 62
4.8.9. Add-in Card Minimum Receiver Path Sensitivity Requirements at 16.0 GT/s ................ 63
4.8.10. System Board Transmitter Path Compliance Eye Diagram at 2.5 GT/s ......................... 65
4.8.11. System Board Transmitter Path Compliance Eye Diagram at 5.0 GT/s ......................... 66
4.8.12. System Board Transmitter Path Compliance Eye Diagram at 8.0 GT/s ......................... 69
4.8.13. System Board Transmitter Path Compliance Eye Diagram at 16.0 GT/s ....................... 72
4.8.14. System Board Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s ............... 74
4.8.15. System Board Minimum Receiver Path Sensitivity Requirements at 5.0 GT/s ............... 75
4.8.16. System Board Minimum Receiver Path Sensitivity Requirements at 8.0 GT/s ............... 77
4.8.17. System Board Minimum Receiver Path Sensitivity Requirements at 16.0 GT/s ............. 78
5. 150 W, 225 W, AND 300 W ADD-IN CARD POWER .......................................................... 79
5.1. 150 W Add-in Card Power-Up Sequencing ................................................................. 81
5.2. 225 W and 300 W Add-in Card Power-Up Sequencing ............................................... 83
6. CARD CONNECTOR SPECIFICATION .............................................................................. 87
6.1. Connector Pinout ........................................................................................................ 87
6.2. Connector Interface Definitions .................................................................................. 90
6.3. Signal Integrity Requirements and Test Procedures ................................................... 96
6.3.1. Signal Integrity Requirements ......................................................................................... 96
6.3.2. Signal Integrity Requirements and Test Procedures for 2.5 GT/s Support ..................... 96
6.3.3. Signal Integrity Requirements and Test Procedures for 5.0 GT/s Support ..................... 99
6.3.3.1 Test Fixture Requirements .................................................................... 101
6.3.4. Signal Integrity Requirements and Test Procedures for 8.0 GT/s Support ................... 101
6.3.4.1 Test Fixture Requirements .................................................................... 103
6.3.5. Signal Integrity Requirements and Test Procedures for 16.0 GT/s Support ................. 103
6.3.5.1 Test Fixture Requirements .................................................................... 106
6.4. Connector Environmental and Other Requirements.................................................. 109
6.4.1. Environmental Requirements ........................................................................................ 109
6.4.2. Mechanical Requirements ............................................................................................. 111
6.4.3. Current Rating Requirement ......................................................................................... 111
6.4.4. Additional Considerations .............................................................................................. 112
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