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PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV 1.1
60
5. Connector Specification
A family of PCI Express vertical edge card connectors supports x1, x4, x8, and x16 Link widths to
suit different bandwidth requirements. These connectors support the PCI Express signal and power
requirements, as well as auxiliary signals used to facilitate the interface between system board and
add-in card hardware. This chapter defines the connector mating interfaces and footprints, as well
5
as the electrical, mechanical, and environmental requirements.
5.1. Connector Pinout
Table 5-1 shows the pinout definition for the x1, x4, x8, and x16 PCI Express connectors. The
auxiliary pins are identified in the shaded areas.
Table 5-
15-1: PCI Express Connectors Pinout
Side B Side A
Pin
#
Name Description Name Description
1 +12V 12 V power PRSNT1#
Hot-Plug presence
detect
2 +12V 12 V power +12V 12 V power
3 +12VRSVD 12 V powerReserved +12V 12 V power
4 GND Ground GND Ground
5 SMCLK
SMBus (System
Management Bus) clock
JTAG2
TCK (Test Clock), clock
input for JTAG interface
6 SMDAT
SMBus (System
Management Bus) data
JTAG3 TDI (Test Data Input)
7 GND Ground JTAG4 TDO (Test Data Output)
8 +3.3V 3.3 V power JTAG5
TMS (Test Mode
Select)
9 JTAG1
TRST# (Test Reset)
resets the JTAG
interface
+3.3V 3.3 V power
10 3.3Vaux 3.3 V auxiliary power +3.3V 3.3 V power
11 WAKE#
Signal for Link
reactivation
PERST# Fundamental reset
5

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV 1.1
61
Side B Side A
Pin
#
Name Description Name Description
Mechanical key
12 RSVD Reserved GND Ground
13 GND Ground REFCLK+
14 PETp0 REFCLK-
Reference clock
(differential pair)
15 PETn0
Transmitter differential
pair, Lane 0
GND Ground
16 GND Ground PERp0
17 PRSNT2# Hot-Plug presence detect PERn0
Receiver differential
pair, Lane 0
18 GND Ground GND Ground
End of the x1 connector
19 PETp1 RSVD
20 PETn1
Transmitter differential
pair, Lane 1
GND Ground
21 GND Ground PERp1
22 GND Ground PERn1
Receiver differential
pair, Lane 1
23 PETp2 GND Ground
24 PETn2
Transmitter differential
pair, Lane 2
GND Ground
25 GND Ground PERp2
26 GND Ground PERn(2)
Receiver differential
pair, Lane 2
27 PETp3 GND Ground
28 PETn0
Transmitter differential
pair, Lane 3
GND Ground
29 GND Ground PERp3
30 RSVD Reserved PERn3
Receiver differential
pair, Lane 3
31 PRSNT2# Hot-Plug presence detect GND Ground
32 GND Ground RSVD Reserved
End of the x4 connector
33 PETp4 RSVD Reserved
34 PETn4)
Transmitter differential
pair, Lane 4
GND Ground
35 GND Ground PERp4
36 GND Ground PERn4
Receiver differential
pair, Lane 4
37 PETp5 GND Ground
38 PETn5
Transmitter differential
pair, Lane 5
GND Ground

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV 1.1
62
Side B Side A
Pin
#
Name Description Name Description
39 GND Ground PERp5
40 GND Ground PERn5
Receiver differential
pair, Lane 5
41 PETp6 GND Ground
42 PETn6
Transmitter differential
pair, Lane 6
GND Ground
43 GND Ground PERp6
44 GND Ground PERn6
Receiver differential
pair, Lane 6
45 PETp7 GND Ground
46 PETn7
Transmitter differential
pair, Lane 7
GND Ground
47 GND Ground PERp7
48 PRSNT2# Hot-Plug presence detect PERn7
Receiver differential
pair, Lane 7
49 GND Ground GND Ground
End of the x8 connector
50 PETp8 RSVD Reserved
51 PETn8
Transmitter differential
pair, Lane 8
GND Ground
52 GND Ground PERp8
53 GND Ground PERn8
Receiver differential
pair, Lane 8
54 PETp9 GND Ground
55 PETn9
Transmitter differential
pair, Lane 9
GND Ground
56 GND Ground PERp9
57 GND Ground PERn9
Receiver differential
pair, Lane 9
58 PETp10 GND Ground
59 PETn10
Transmitter differential
pair, Lane 10
GND Ground
60 GND Ground PERp10
61 GND Ground PERn10
Receiver differential
pair, Lane 10
62 PETp11 GND Ground
63 PETn11
Transmitter differential
pair, Lane 11
GND Ground
64 GND Ground PERp11
65 GND Ground PERn11
Receiver differential
pair, Lane 11
66 PETp12 GND Ground
67 PETn12
Transmitter differential
pair, Lane 12
GND Ground

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV 1.1
63
Side B Side A
Pin
#
Name Description Name Description
68 GND Ground PERp12
69 GND Ground PERn12
Receiver differential
pair, Lane 12
70 PETp13 GND Ground
71 PETn13
Transmitter differential
pair, Lane 13
GND Ground
72 GND Ground PERp13
73 GND Ground PERn13
Receiver differential
pair, Lane 13
74 PETp14 GND Ground
75 PETn14
Transmitter differential
pair, Lane 14
GND Ground
76 GND Ground PERp14
77 GND Ground PERn14
Receiver differential
pair, Lane 14
78 PETp15 GND Ground
79 PETn15
Transmitter differential
pair, Lane 15
GND Ground
80 GND Ground PERp15
81 PRSNT2# Hot-Plug presence detect PERn15
Receiver differential
pair, Lane 15
82 RSVD Reserved GND Ground
End of the x16 connector
The following points should be noted:
The pins are numbered as shown in Figure 5-3 in ascending order from the left to the right, with
side A on the top of the centerline and side B on the bottom of the centerline.
The PCI Express interface pins PETpx, PETnx, PERpx, and PERnx are named with the
following convention: “PE” stands for PCI Express high speed, “T” for Transmitter, “R” for
5
Receiver, “p” for positive (+), and “n” for negative (-).
By default, PETpx and PETnx pins (the Transmitter differential pair of the connector) shall be
connected to the PCI Express Transmitter differential pair on the system board, and to the PCI
Express Receiver differential pair on the add-in card.
By default, PERpx and PERnx pins (the Receiver differential pair of the connector) shall be 10
connected to the PCI Express Receiver differential pair on the system board, and to the PCI
Express Transmitter differential pair on the add-in card.
However, the “"p”" and “"n”" connections may be reversed to simplify PCB trace routing and
minimize vias if needed. All PCI-Express Receivers incorporate automatic Lane Polarity
Inversion as part of the Link Initialization and Training and will correct the polarity
15
independently on each Lane. Refer to Section 4.2.4. of the PCI Express Base Specification,
Revision 1.1.

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV 1.1
64
If the component on the system board or add-in card does not support the optional PCI
Express Lane Reversal functions, they must connect each Transmitter and Receiver Lane to the
add-in card connector lanes as shown in Table 5-
1. For example, a x4 component must connect
Lane 0 to 0, Lane 1 to 1, Lane 2 to 2, and Lane 3 to 3.
If the component on the system board or add-in card supports the optional PCI Express Lane 5
Reversal function, it may connect each Transmitter and Receiver Lane to the add-in card
connector lanes as shown in Table 5-
1 or it may connect the Transmitter and Receiver lanes
using a reversed Lane ordering. Either Lane ordering may be used to simplify PCB trace routing
and minimize vias. However, the transmitting and receiving lanes must be connected with the
same Lane ordering. For example, a x4 component may connect Lane 0 to 0, Lane 1 to 1, Lane
10
2 to 2, and Lane 3 to 3 or it may connect Lane 0 to 3, Lane 1 to 2, Lane 2 to 1, and Lane 3 to 0.
The connectors and the add-in cards are keyed such that smaller add-in cards can be put in
larger connectors. For example, an
x1 card can be inserted into the x4, x8, and x16 connectors.
This is referred to as up-plugging.
Adjacent differential pairs are separated by two ground pins to manage the connector crosstalk. 15
See Chapter 2 for auxiliary signals description and implementation, except the +3.3Vaux and
PRSNT1# and PRSNT2# pins. The requirements for +3.3Vaux are discussed in Chapter 4 and
presence detect is discussed in Chapter 3.
PRSNT1# and PRSNT2# pins are for card presence detect. One present detect pin at each end
of a connector guarantees that at least one of the present detect pins is last-mate/first-break.
20
More than two PRSNT2# pins in the x4, x8, and x16 PCI Express connectors are for the
purpose of supporting up-plugging. See Chapter 3 for detailed discussions on presence detect.
The sequential mating for Hot-Plug is accomplished by staggering the edge fingers on the add-in
card, as shown in Section 5.2. Detailed requirements on Hot-Plug are covered in Chapter 3.
Power pins (+3.3V, +3.3Vaux, and +12V) are defined based on the PCI Express power delivery 25
requirements specified in Chapter 4, with the connector contact carrying capability being 1.1 A
per pin. The power that goes through the connector shall not exceed the maximum power
specified for a given add-in card size, as defined in Table 4-
3.
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