PCI Express Base Specification 5.0 .pdf

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PCI Express Base Specification Revision 5.0 version 1.0
5.0-1.0-PUB-PCl Express Base Specification Revision 5.0 Version 1.0 Table of contents 1. Introduction Q 1.1 A Third Generation I/o Interconnect. 2 PCI Express Link .·········.···.······· 90 1.3 PCI Express Fabric Topology...... 92 1.3.1 Root Complex…, …92 1.3.2 Endpoints 93 1.3.2.1 Legacy Endpoint Rules 93 1.3.2.2 PCI Express Endpoint rules...... …94 1.3.2.3 Root Complex Integrated Endpoint Rules………,… ……94 1.3.3 Switch 95 1.3.4 Root Complex Event Collector …96 1.3.5 PCI Express to PCl/PCI-X Bridge....... ………96 1.4 Hardware/ Software Model for Discovery, Configuration and Operation.. 96 1.5 PCI Express Layering Overview. 97 1.5.1 Transaction layer Q 1.5.2 Data Link Layer…..…99 1.5.3 Physical Layer.……… 1.5.4 Layer Functions and Services 100 1.5.4.1 Transaction Layer Services 100 1.5.4.2 Data Link Layer Services. 1.5.4.3 Physical Layer services.. 101 1.5.4.4 Inter-Layer Interfaces ……102 1.5.4.4.1 Transaction /Data Link Interface......... 102 1.5.4.4.2 Data Link/Physical Interface............ ∴102 2. Transaction Layer Specification. 2.1 Transaction Layer overview 103 2.1.1 Address Spaces, Transaction Types, and Usage. ................................................................................104 21.1.1 Memory Transactions..……… 104 2. 1.1.2 1/0 Transactions ··.······· 104 2.1.1.3 Configuration Transactions.. 105 2.1.1.4 Message Transactions 105 2.1.2 Packet format overview 105 2.2 Transaction Layer protocol-Packet Definition 107 2.2.1 Common Packet header fields 107 2.2.2 TLPs with Data Payloads- Rules. ..................................................................................................110 2.2.3 TLP Digest Rule 113 22.4 Routing and Addressing Rules……… …………113 2.2.4.1 Address-Based routing rules.. 113 2242 ID Based Routing Rules…...,.,.,.,.,.,.,…,….…………15 2.2.5 First/Last DW Byte Enables Rules... 117 2.2.6 Transaction Descriptor 119 2.2.6.1 Overview.……...119 22.6.2 Transaction Descriptor- Transaction| D Field....…,……,………….120 2. 2.6.3 Transaction Descriptor -Attributes field …125 2.2.6.4 Relaxed Ordering and id-Based Ordering attributes ....................................................................126 2.,2.6.5 No Snoop Attribute…… 126 Page 3 5.0-1.0-PUB-PCl Express Base Specification Revision 5.0 Version 1.0 2. 2.6.6 Transaction Descriptor-Traffic Class Field..... 127 2.2.7 Memory, 1/0, and Configuration Request Rules 127 2.2.7.1 TPH Rules… 131 228 Message Request rules……,.,,, 133 2.2.8.1 INTX Interrupt Signaling -.. 135 2.2.8.2 Power Management messages ∴139 2.2.8.3 Error Signaling messages 140 22.8.4 Locked Transactions Support.…… .,…,………141 2. 2.8.5 Slot Power Limit Support 142 2.2.8.6 Vendor defined messages …143 2.2.8.6.1 PCI-SIG-Defined VDMs 144 2.2.8.6. 2 LN Messages 145 2.2.8.6. 3 Device Readiness Status(DRS)Message 146 2.2.8.6.4 Function Readiness Status Message 2. 2.8.6.5 Hierarchy ID Message …148 228.7 Ignored messages…… 150 2.2.8.8 Latency Tolerance Reporting(LTR)Message.... ∴150 228.9 Optimized Buffer Flush/Fi(OBFF) Message,.,.,.,.,…,………,….151 2.2.8. 10 Precision Time Measurement 22.9 Completion Rules…………, 153 2.2.10 TLP Prefix Rules 156 22.10.1 Local tlp Prefiⅸ k Processing.… 157 2.2.10.1. 1 Vendor Defined Local TLP Prefix 157 22.10.2End- End TLP Prefix Processing…………………,,…,… .157 2.2.10.21VendordefinedEnd-endTlpPrefixwwwmwwww.159 2.2.10.2.2 Root Ports with End-End TLP Prefix Supported........ 159 2.3 Handling of Received TLPs 160 23.1 Request Handling rules…...............……163 2.3.1.1 Data Return for Read Requests ...................169 23.2 Completion Handling Rules…...….…,…… 175 2. 4 Transaction Ordering................ 177 2.4.1 Transaction Ordering Rules. 177 2.4.2 Update Ordering and Granularity Observed by a Read Transaction .4.s:ts+4.i,s. 181 2.4.3 Update Ordering and Granularity Provided by a Write Transaction .........182 2.5 Virtual Channel (vc) mechanism 182 2.5.1 Virtual Channel 184 2.5.2 TC to VC Mapping... 185 2.5.3 VC and TC rules …186 2.6 Ordering and Receive Buffer Flow Control...........................187 2.6.1 Flow Control rules 18 2.6.1.1 FC Information tracked by transmitter 192 2.6.1.2 FC Information Tracked by receiver 194 2.7 Data Integrity……,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,……,…,…,198 2.7.1 ECRC Rules 198 2.7.2 Error Forwarding.. 202 2.7. 2.1 Error Forwarding Usage Mode ,垂垂垂市音垂垂.垂 202 2.7. 2.2 Rules For Use of data poisoning.... ∴203 2.8 Completion Timeout Mechanisn .204 2.9 Link Status Dependencies 205 2.9.1 Transaction Layer Behavior in DL_ Down Status …205 5.0-1.0-PUB-PCl Express Base Specification Revision 5.0 Version 1.0 2.9.2 Transaction Layer Behavior in DL_Up Status.... 206 2.9.3 Transaction Layer Behavior During Downstream Port Containment. 206 3. Data Link Layer Specification 4。,音面 3.1 Data Link Layer Overview. 209 3,2 Data Link Control and Management State Machine…………………… 210 3.2.1 Data Link Control and Management state Machine rules …211 3 Data Link Feature Exchange………,…,…,… 3. 4 Flow Control initialization protocol 215 3.4.1 Flow Control initialization state Machine rules 215 3.4.2 Scaled flow control 220 3.5 Data Link Layer Packets(DLLPs) ∴1221 3.5.1 Data Link Layer Packet Rules. .........................221 3.6 Data Integrity Mechansisms 227 3.6.1 Introduction 227 3.6.2 LCRC, Sequence Number, and Retry Management(TLP Transmitter 228 3.6.2.1 LCRC and Sequence number rules (tlp transmitter)............ 228 3.6.2.2 Handling of received DLLPs …235 3.6.3 LCRC and Sequence Number(tLp receiver)...... 4音 238 3631 LCRC and Sequence Number Rules( TLP Receiver)……,,…,…,……………,1239 4. Physical Layer Logical Block....... 245 4.1 Introduction 245 4.2 Logical Sub-block..... 245 4.2.1 Encoding for 2.5 GT/s and 5.0 GT/s Data Rates..... 246 4. 1. 1 Symbol Encoding. 246 4.2.1.1.1 Serialization and De-serialization of data .m..m..mw.m.m... 246 4.2.1.1.2 Special Symbols for Framing and Link Management(K Codes) 面4,4音面 247 4.2. 1.1.3 8b/10b Decode rules.................... 4.2.1.2 Framing and Application of Symbols to Lanes.. 249 4.213 Data Scrambling…,………,……………252 4.2.2 Encoding for 8.0 GT/s and Higher Data Rates .....253 4.2.2.1 Lane Level Encoding...... 254 4.2.2.2 Ordered set blocks 256 4.2.2.2.1 Block Alignment.............................256 4.2.2.3 Data blocks 257 4.2.2.3.1 Framing Tokens…...… ….258 4.2.2.3.2 Transmitter Framing Requirements………………………………… ….263 4. 2.2.3.3 Receiver Framing Requirements 264 4.22.34 Recovery from Framing Errors…… 266 4.2.2.4 Scrambling……………… 267 4.2.2.5 Precoding…...,.........,.,….,…,…,,……………………272 4. 2.2.6 Loopback with 128b/130b Code 274 4.2.3 Link Equalization Procedure for 8.0 GT/s and Higher Data Rates.....................274 4.2.3.1 Rules for transmitter coefficients 4.2.3.2 Encoding of Presets …………287 4.2.4 Link Initialization and training . 4.2.4.1 Training Sequences…,,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,,288 4.24.2 Alternate Protocol Negotiation……… 4.2.4.3 Electrical ldle Sequences(elos ∴,301 Page 5 5.0-1.0-PUB-PCl Express Base Specification Revision 5.0 Version 1.0 4.2.4.4 Inferring Electrical ldle... 305 4.2.4.5 Lane polarity Inversion 音;非看垂垂垂音音非垂垂音音非非垂垂非,垂垂垂 306 4.2.4.6 Fast Training Sequence(Fts) 306 4.2.4.7 Start of Data Stream Ordered Set(sDs Ordered Set 308 4.2.4. 8 Link Error Recovery.......... 4.2.4.9 Reset. 309 4.2.4.9.1 Fundamental reset 309 4.2.4.9.2 Hot reset...1310 4.2.4.10 Link Data Rate Negotiation.................310 4.2.4.11 Link Width and Lane sequence Negotiation 310 4.2.4.11.1 Required and Optional Port Behavior.. ……310 4.2.4.12 Lane-to-Lane de-skew 4.2.4.13 Lane Vs Link Training... 312 4.2.5 Link Training and Status State Machine(LTSSM)Descriptions 312 4.2.5.1 Detect overview∴……1313 4.2.5.2 Polling overview.............. …313 4.2.5.3 Configuration Overview.............. 313 4.2.5.4 Recovery overview……………,……………,…,………………1313 4.2.5.5L0 Overview.,,1314 4.2.5.6 LOs Overview ∴314 4.2.5.7L1 Overview…………1314 4.2.5. 8 L2 Overview 4.2.5 9 Disabled overview ··.·.····· 314 4. 2.5.10 Loopback Overview. ……314 4.2.5.11 Hot reset overview 4.2.6 Link Training and Status State Rules . 315 4261 Detect 317 4.2.6.1. 1 Detect Quiet ……317 4.2.6.1.2 Detect Active …1…1318 4.2.6.2 Polling 4.2.6.2. 1 Polling.Active.... 319 4.2.6.2.2 Polling Compliance. 320 4.2.6.2.3 Polling Configuration... 324 4.2.6.2. 4 Polling. Speed.. 1325 4.2.6.3 Configuration 325 4.2.6.3.1 Configuration. Linkwidth.stat….…...........…….……326 4.2.6.3. 1.1 Downstream lanes 326 4.2.6.3.1.2 Upstream Lanes…………….….….….….….….….….…….….….…….……………27 4.2.6.3.2 Configuration Linkwidth Accept ...329 4.2.6.3.2.1 Downstream lanes…… 329 4.2.6.3.2.2 Upstream lanes 330 4.2.6.33 Configuration. Lanenum. Accept..…,…,… ,332 4.26.3.3.1 Downstream 4.2.6.3.3.2 Upstream Lanes……………,…,…… 133 4.2.6.3. 4 Configuration. Lanenum Wait 4263, 4.1 Downstream lanes 333 4.2.6.3. 4.2 Upstream lanes ∴334 4.2.6.3.5 Configuration Complete 334 4.2.6.3.5.1 Downstream lanes 334 4.2.6.3.5.2 Upstream Lanes…………,,…,…,…,…,…,…,…,…,…,…,,…,,…,…,…,…,,……,…,,…………36 5.0-1.0-PUB-PCl Express Base Specification Revision 5.0 Version 1.0 4.2.6.3.6 Configuration Idle 337 4.2.6.4 Recovery…… 4.2.6.4.1 Recovery RcvrLock.... 340 4.2.6.4.2RecoveryEqualization........ 346 42.64.2.1 Downstream lanes 347 4.2.6.4.2.1.1 Phase 1 of Transmitter equalization …347 4.2.6.4.2.1.2 Phase 2 of Transmitter Equalization 349 4.2.6.4.2.1.3 Phase 3 of Transmitter equalization …350 4.2.6.4.2.2 Upstream Lanes...,...,.,,,,,,, 352 4.2.6.4.2.2.1 Phase 0 of Transmitter Equalization 352 4.2.6.4.2.2.2 Phase l of Transmitter equalization 353 4.2.6.4.2.2.3 Phase 2 of Transmitter equalization ……354 4.2.6.4.2.2.4 Phase 3 of Transmitter Equalization......... 356 4.2.6.4.3 Recovery Speed 357 4.2.6.4.4 Recovery Rcvrcfg... 358 4.2.6.4.5 Recovery. Idle..............363 4.2.6.5L0 366 4.2.6.6L0s………,,………67 4.2.6.6.1 Receiver los 368 4.2.6.6.1.1RX_L0s. Entry………… 368 4.2.6.6.1.2RxL0s.dle. 4.2.6.6.1.3RX_L0sFTS…,… 4.2.6.6.2 Transmitter LOs 369 4.2.6.52.1TX_L0s. Entry……… ……69 4.2.662.2TXL0s|dle 369 4.2.6.62.3TxL0sFTS 369 4.2.6.7L1 371 4.2.6.7.1L1. Entry…… ….371 4.2.6.72L1|de ....1371 4.2.6.8L2 373 4.2.6.8.1L2.de 373 4. 2.6.8.2 L2 TransmitWake 374 4.2.6.9 Disabled..…74 4.26.10 Loopback……...…..,.,.,,.,,,.,,,........175 4.2.6.10.1 Loopback Entry... …375 4.2.6.10.2 Loopback. Active….......... 378 4.2.6.10.3 Loopback Exit ........... 379 4.2.6.11 Hot reset 4.2.7 Clock Tolerance Compensation......................381 4.2.7.1 SKP Ordered Set for 8b/10b Encoding. 382 4.2.7. 2 SKP Ordered Set for 128b/130b Encoding 382 4.2.7.3 Rules for transmitters 386 4.2.7.4 Rules for receivers . 4.2.8 Compliance Pattern in 388 4.2.9 Modified Compliance Pattern in 8b/10b Encoding .. 389 4.2.10 Compliance Pattern in 128b/130b Encoding.... 390 4.2.11 Modified Compliance Pattern in 128b/130b Encoding 393 4.2.12 Jitter Measurement Pattern in 128b/130b.. 393 4.2.13 Lane Margining at Receiver 394 4.2.13.1 Receiver num ber, Margin Type, Usage Mode, and Margin Payload Fields…………,,………394 Page 7 5.0-1.0-PUB-PCl Express Base Specification Revision 5.0 Version 1.0 4.2.13.1.1 Step Margin EXecution Status 399 4.2.13. 1.2 Margin Payload for Step Margin Commands 399 4. 2.13.2 Margin Command and response flow 400 4. 2.13.3 Receiver Margin Testing Requirements 403 4.3 Reimers 407 4.3.1 Retimer Requirements……… 408 4.3.2 Supported Retimer Topologies 409 4.3.3 Variables,,,,m..w,m.410 4.3.4 Receiver Impedance Propagation Rules 411 4.3.5 Switching Between Modes 411 4.3.6 Forwarding rules…………………… 411 4.3.6.1 Forwarding Type rules........412 43 6.2 Orientation and lane numbers rules 412 4,3.6,3Electricalldleexitruleswwww..wwwwwwwwwwwwm413 4.3.6.4 Data Rate Change and Determination 4.3.6.5 Electrical ldle Entry Rules…… 416 4.3.6.6 Transmitter Settings Determination Rules.. 417 43. 6.7 Ordered set modification rules 418 43.6.8DLLP,TLP,andLogicadleModificationRues....,,420 43.6.98b/10 o Encoding rules…,,…… 421 4.3.6,108b/10 o Scrambling Rules…............,,,.,,,…,…,4.21 4.3.6.11 Hot reset rules.……… 421 4.3.6.12 Disable link rules 421 43.6.13 Loopback…....,.,,,, …….422 4.3.6. 14 Compliance Receive rules.......... 423 4.3.6. 15 Enter Compliance rules 424 4. 3. 7 Execution Mode rules 427 43.71 CompLoad Board Rules......,..,,…,…… ··· .427 4.3.7.1.1 CompLoad Board.Enty…..............27 4.3.7.1.2 CompLoad Board. Pattern…… 427 4.3.7.1.3 CompLoad Board Exit 4垂垂看音垂音音B鲁4垂 428 4.3.7.2 Link Equalization Rules………,,,, 429 4.3.7.2.1 Downstream lanes 429 4.3.7.2.1.1 Phase2…429 437.2.1.2 Phase 3 Active mmw. 4.3,7.21.3 Phase 3 Passive 429 4.3. 7.2.2 Upstream Lanes............. 430 4.3.7.2.2.1 Phase 2 Active 430 4.3. 7.2.2.2 Phase 2 Passive 430 4.3,7.2.2.3 Phase3 ,看垂4垂 430 4.3.7.2.3 Force Timeout 4.3.7.3 Slave Loopback…… 431 4.3.7.3. 1 Slave Loopback Entry ........ 431 4.3.7.3.2 Slave Loopback Active... …432 4.3. 7.3.3 Slave Loopback Exit...... ·······丰 432 4.3.8 Retimer Latency………………… 432 4.3.8.1 Measurement 432 4.3.8.2 Maximum Limit on Retimer Latency 432 4.3.8.3 Impacts on Upstream and downstream Ports 2433 4.3.9SR|S 433 5.0-1.0-PUB-PCl Express Base Specification Revision 5.0 Version 1.0 4.3.10 L1 PM Substates Support 4.3.11 Retimer Configuration Parameters 9436 43, 11.1 Global Parameters 437 4.3.11.2 Per Physical Pseudo Port Parameters…………,,…… 垂垂·垂 437 4.3.12 In Band Register Access 438 5. Power Management…. ……439 5.1 Overview ∴439 5.2 Link State Power Management. ∴1440 5.3 PCl-PM Software Compatible mechanisms 444 5.3.1 Device Power Management States(D-States)of a Function.. ,4 5.3.1.1D0 State... -45 5.3.1.2D1 State..…,, 445 5.3.1.3 D2 State 445 5.3.1.4 D3 State 446 5.3.1.4. 1 D3Hot state 447 5.3.1.4.2D3 Cold state..... 448 5.3.2 PM Software Control of the Link Power Management State..... 449 53.2.1 Entry into the Ll State……. 450 5.3.2.2 Exit from L1 State 453 5.3.2.3 Entry into the L2 /L3 Ready State Bassaaaa4 sasssa 454 5.3.3 Power Management Event Mechanisms 454 5.3.3.1 Motivation 454 53.32 Link Wakeup….....,…… ,看垂4垂 455 5.3.3.2. 1 PME Synchronization.......... ·音,,垂。番4垂 456 5.3.3.3PM_ PME Messages.......,,…,…,…, ∴458 5.3.3.3.1 PM_PME"Backpressure"Deadlock Avoidance 458 5.3.3, 4 PME Rules 匚Q 5.3.3.5 PM_PME Delivery State Machine. 459 54 Native pc| Express Power Management Mechanisms…..,.,.,…,.,,…….…,460 5.4.1 Active State Power Management (ASPM) 460 5.4.1.1 LOs ASPM State 462 5.4.1.1.1 Entry into the LOs State 463 5.4.1.1.2 Exit from the los state. .....m...m.o..m.. 464 5.4.1.2 L1 ASPM State 464 5.4.1.2. 1 ASPM Entry into the Ll State 465 5.4.1.2.2 Exit from the l1 State…… 471 5413 ASPM Configuration…… 474 5.4.1.3.1 Software Flow for Enabling or Disabling ASPM 477 5 L1 PM Substates …478 5.5.1 Entry conditions for L1 PM Substates and L1.0 Requirements 面垂4 482 55.2L1.1 Requirements…...................………….483 55.21 Exit from l1.1… 483 5.5.3L1.2 Requirements.…....,……… 5.5.3.1L1.2. Entry...,,… 485 5.5.3.2L1.2.lde................… ……….486 5.5.3.3L1.2.Exit ..·····::::····:·· 486 5.5.3.3.1 Exit from l1.2 487 5.5.4 L1 PM Substates Configuration 488 5.5.5 L1 PM Substates Timing Parameters 4垂·垂 Page 9 5.0-1.0-PUB-PCl Express Base Specification Revision 5.0 Version 1.0 5.5.6 Link Activation 56 Auxiliary Power Support......,,,…,…,…,… ∴490 5.7 Power Management system messages and dlls 490 5. 8 PCI Function power state transitions 491 5. 9 State Transition Recovery Time Requirements 492 5.10 PCI Bridges and Power Management 493 5.10.1 Switches and PCI Express to PCI Bridges .494 5.11 Power Management Events…….….….….….…….……494 6. System Architecture 495 6. 1 Interrupt and Pme Support 495 6.1.1 Rationale for PCI Express Interrupt 6.1.2 PCl-compatible INTx Emulation 495 6.1.3 IN TX Emulation Software model 496 6.1.4 MSI and MSI-X Operation....... 量着4, 496 6.1.4.1 MSI Configuration 497 6142MS| X Configuration...,.,…… 6.1.4.3 Enabling Operation...... …499 6.1.4.4 Sending Messages........ 500 6.1.4.5 Per-vector Masking and Function Masking………500 6. 1.4.6 Hardware/Software Synchronization 01 6.1.4.7 Message Transaction Reception and Ordering Req 1503 1.5 PME Support.....................503 6.1.6 Native Pme Software model 503 6.1.7 Legacy PME Software Model…… 504 6.1.8 Operating System Power Management Notification 504 6.1.9 PME Routing Between PCI Express and PCI Hierarchies.... ·· 504 62 Error Signaling and Logging……… .1505 6.2.1 Scope…..,. …505 6.2.2 Error Classification 505 6.2.2.1 Correctable errors 506 6.2.2.2 Uncorrectable errors ∴.507 6.2.2.2. 1 Fatal Errors 507 6.2.2.2.2 Non-Fatal Errors 2507 6,2.3 Error signaling…………………… 507 6.2.3.1 Completion Status 507 6.2.3.2 Error Messages…….… 507 6.2.3.2.1 Uncorrectable Error Severity Programming (Advanced Error Reporting). 6.2.3.2.2 Masking Individual Errors 509 6.2.3.2.3 Error Pollution 509 6.2.3.2.4 Advisory Non-Fatal Error Cases 510 6.2.3.2.4.1 Completer Sending a Completion with UR/CA Status .510 6.2.3.24.2 Intermediate receiver……… ∴…………,…511 6.2.3.2.4.3 Ultimate PCI Express Receiver of a Poisoned TLP... 511 6.2.3.2.4. Requester with Completion Timeout ·.··:· 512 6.2.3.2.4.5 Receiver of an Unexpected Completion 512 62.3.2.5 Requester Receiving a Completion with UR/ CA Status….......………1512 6.2.3.3 Error Forwarding(Data Poisoning 512 6234 Optional Error Checking….....….…….………1513 6. 2. 4 Error Logging.... 513 Page 10

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