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DS512 April 24, 2012 www.xilinx.com 1

Product Specification

United States and other countries. All other trademarks are the property of their respective owners.

Introduction

The Xilinx LogiCORE™ IP Block Memory Generator

(BMG) core is an advanced memory constructor that

generates area and performance-optimized memories

using embedded block RAM resources in Xilinx

FPGAs. Available through the CORE Generator™

software, users can quickly create optimized memories

to leverage the performance and features of block

RAMs in Xilinx FPGAs.

The BMG core supports both Native and AXI4

interfaces.

The Native interface BMG core configurations support

the same standard BMG functions delivered by

previous versions of the Block Memory Generator (up

to and including version 4.3). Port interface names are

identical.

The AXI4 interface configuration of the BMG core is

derived from the Native interface BMG configuration

and adds an industry-standard bus protocol interface

to the core. Two AXI4 interface styles are available:

AXI4 and AXI4-Lite.

For details on the features of each interface, see

Features.

LogiCORE IP Block

Memory Generator v7.1

DS512 April 24, 2012 Product Specification

LogiCORE IP Facts

Core Specifics

Supported

Device

Families

(1)

1. For the complete list of supported devices, see Table 1, page 3 and

the release notes

for this core.

Zynq-7000, Artix-7, Virtex-7, Kintex-7,

Virtex-6, Virtex-5, Virtex-4, Spartan-6,

Spartan-3E/XA, Spartan-3/XA,

Spartan-3A/3AN/3A DSP

Supported User

Interfaces

AXI4, AXI4-Lite

Block RAM Varied, based on core parameters

DCM None

BUFG None

IOBs/

Transceivers

None

PPC None

IOB-FF/TBUFs None

Provided with Core

Documentation

Product Specification

Migration Guide

(2)

2. The Migration Guide provides instructions for converting designs

that contain instances of either Legacy LogiCORE IP 6.x Single or

Dual Port Block Memory, or older versions of the Block Memory

Generator to the latest version of the Block Memory Generator.

Design File

Formats

NGC Netlist

Example Design VHDL

Demonstration

Test Bench

VHDL

Design Tool Requirements

Xilinx

Implementation

Tools

ISE v14.1

Simulation

(3)

3. For the supported versions of the tools, see the ISE Design Suite

14: Release Notes Guide.

Mentor Graphics ModelSim

VHDL Structural

Verilog Structural

VHDL Behavioral

(4)

Verilog Behavioral

(4)

4. Behavioral models do not precisely model collision behavior. See

Simulation Models, page 56 for details.

Synthesis XST

Support

Provided by Xilinx, Inc.

LogiCORE IP Block Memory Generator v7.1

2 www.xilinx.com DS512 April 24, 2012

Product Specification

Features

Features Common to the Native Interface and AXI4 BMG Cores

• Optimized algorithms for minimum block RAM resource utilization or low power utilization

• Configurable memory initialization

• Individual Write enable per byte in Zynq™-7000, Kintex™-7, Virtex®-7, Virtex-6, Virtex-5, Virtex-

4, Spartan®-6, and Spartan-3A/XA DSP with or without parity

• Optimized VHDL and Verilog behavioral models for fast simulation times; structural simulation

models for precise simulation of memory behaviors

• Selectable operating mode per port: WRITE_FIRST, READ_FIRST, or NO_CHANGE

• Smaller fixed primitive configurations are now possible in Spartan-6 devices with the introduction

of the new Spartan-6 device 9K primitives

• Lower data widths for Zynq-7000, 7 series, and Virtex-6 devices in SDP mode

• VHDL example design and demonstration test bench demonstrating the IP core design flow,

including how to instantiate and simulate it

Native Block Memory Generator Specific Features

• Generates Single-port RAM, Simple Dual-port RAM, True Dual-port RAM, Single-port ROM, and

Dual-port ROM

• Supports data widths from 1 to 4096 bits and memory depths from 2 to 9M words (limited only by

memory resources on selected part)

• Configurable port aspect ratios for dual-port configurations and Read-to-Write aspect ratios in

Virtex-6, Virtex-5, and Virtex-4 FPGAs

• Supports the built-in Hamming Error Correction Capability (ECC) available in Zynq-7000, 7

series, Virtex-6 and Virtex-5 devices for data widths greater than 64 bits. Error injection pins in

Zynq-7000, 7 series, and Virtex-6 allow insertion of single and double-bit errors

• Supports soft Hamming Error Correction (Soft ECC) in Zynq-7000, 7 series, Virtex-6, and Spartan-

6 devices for data widths less than 64 bits.

• Option to pipeline DOUT bus for improved performance in specific configurations

• Choice of reset priority for output registers between priority of SR (Set Reset) or CE (Clock Enable)

in Zynq-7000, 7 series, Virtex-6, and Spartan-6 families

• Asynchronous reset in Spartan-6 devices

• Performance up to 450 MHz

AXI4 Interface Block Memory Generator Specific Features

• Supports AXI4 and AXI4-Lite interface protocols

• AXI4 compliant Memory and Peripheral Slave types

• Independent Read and Write Channels

• Zero delay datapath

• Supports registered outputs for handshake signals

• INCR burst sizes up to 256 data transfers

• WRAP bursts of 2, 4, 8, and 16 data beats

• AXI narrow and unaligned burst transfers

• Simple Dual-port RAM primitive configurations

DS512 April 24, 2012 www.xilinx.com 3

Product Specification

LogiCORE IP Block Memory Generator v7.1

• Performance up to 300 MHz

• Supports data widths from up to 256 bits and memory depths from 2 to 9 M words (limited only

by memory resources on selected part)

• Symmetric aspect ratios

• Asynchronous active low reset

Native Block Memory Generator Feature Summary

Overview

The Block Memory Generator core uses embedded Block Memory primitives in Xilinx FPGAs to extend

the functionality and capability of a single primitive to memories of arbitrary widths and depths.

Sophisticated algorithms within the Block Memory Generator core produce optimized solutions to

provide convenient access to memories for a wide range of configurations.

The Block Memory Generator has two fully independent ports that access a shared memory space. Both

A and B ports have a Write and a Read interface. In Zynq-7000, 7 series, Virtex-6, Virtex-5 and Virtex-4

FPGA architectures, each of the four interfaces can be uniquely configured with a different data width.

When not using all four interfaces, the user can select a simplified memory configuration (for example,

a Single-Port Memory or Simple Dual-Port Memory) to reduce FPGA resource utilization.

The Block Memory Generator is not completely backward-compatible with the discontinued legacy

Single-Port Block Memory and Dual-Port Block Memory cores; for information about the differences,

see Compatibility with Older Memory Cores, page 87.

Applications

The Block Memory Generator core is used to create customized memories to suit any application.

Typical applications include:

• Single-port RAM: Processor scratch RAM, look-up tables

• Simple Dual-port RAM: Content addressable memories, FIFOs

• True Dual-port RAM: Multi-processor storage

• Single-port ROM: Program code storage, initialization ROM

• Dual-port ROM: Single ROM shared between two processors/systems

Supported Devices

Table 1 shows the families and sub-families supported by the Block Memory Generator.

Table 1: Supported FPGA Families and Sub-Families

FPGA Family Sub-Family

Spartan-3

Spartan-3E

Spartan-3A

Spartan-3AN

Spartan-3A DSP

Spartan-6 LX/LXT

DS512 April 24, 2012 www.xilinx.com 5

Product Specification

LogiCORE IP Block Memory Generator v7.1

• In all supported device families, the A port width may differ from the B port width by a factor of 1,

2, 4, 8, 16, or 32.

• In Zynq-7000, 7 series, Virtex-6, Virtex-5 and Virtex-4 FPGA-based memories, the Read width may

differ from the Write width by a factor of 1, 2, 4, 8, 16, or 32 for each port. The maximum ratio

between any two of the data widths (

DINA, DOUTA, DINB, and DOUTB) is 32:1.

Optional Byte-Write Enable

In Zynq-7000, 7 series, Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A/3A DSP FPGA-based

memories, the Block Memory Generator core provides byte-Write support for memory widths which

are multiples of eight (no parity) or nine bits (with parity).

Optional Output Registers

The Block Memory Generator provides two optional stages of output registering to increase memory

performance. The output registers can be chosen for port A and port B separately. The core supports the

Zynq-7000, 7 series, Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A DSP embedded block RAM

registers as well as registers implemented in the FPGA fabric. See Output Register Configurations,

page 97 for more information about using these registers.

Optional Pipeline Stages

The core provides optional pipeline stages within the MUX, available only when the registers at the

output of the memory core are enabled and only for specific configurations. For the available

configurations, the number of pipeline stages can be 1, 2, or 3. For detailed information, see Optional

Pipeline Stages, page 35.

Optional Enable Pin

The core provides optional port enable pins (ENA and ENB) to control the operation of the memory.

When deasserted, no Read, Write, or reset operations are performed on the respective port. If the enable

pins are not used, it is assumed that the port is always enabled.

Optional Set/Reset Pin

The core provides optional set/reset pins (RSTA and RSTB) for each port that initialize the Read

output to a programmable value.

Memory Initialization

The memory contents can be optionally initialized using a memory coefficient (COE) file or by using the

default data option. A COE file can define the initial contents of each individual memory location, while

the default data option defines the initial content of all locations.

Hamming Error Correction Capability

Simple Dual-port RAM memories support the built-in FPGA Hamming Error Correction Capability

(ECC) available in the Zynq-7000, 7 series, Virtex-6 and Virtex-5 FPGA block RAM primitives for data

widths greater than 64 bits. The BuiltIn_ECC (ECC) memory automatically detects single- and double-

bit errors, and is able to auto-correct the single-bit errors.

For data widths of 64 bits or less, a soft Hamming Error Correction implementation is available for

Zynq-7000, 7 series, Virtex-6, and Spartan-6 designs.

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