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The Xilinx LogiCORE IP DisplayPort interconnect protocol is designed for transmission and reception of serial-digital video at two standard rates of 1.62 Gbps and 2.7 Gbps for consumer and professional displays.
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DS735 July 23, 2010 www.xilinx.com 1
Product Specification
© 2009-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
Introduction
The Xilinx LogiCORE™ IP DisplayPort™ interconnect
protocol is designed for transmission and reception of
serial-digital video at two standard rates of 1.62 Gbps
and 2.7 Gbps for consumer and professional displays.
DisplayPort is a high-speed serial interface standard
supported by industry leaders in consumer HDTV, PC
laptop and PC Monitors. This protocol replaces DVI
and HDMI outside and LVDS inside the box for higher
resolution, higher frame rate and color bit depth dis-
play. DisplayPort offers a smaller design, two-way
interaction, improved signal integrity, and reduced
EMI while providing faster speed.
The Xilinx DisplayPort solution is fully compliant to
the VESA DisplayPort Standard v1.1a specification
[Ref 1]. Spartan®-6, Virtex®-6 and Virtex-5 families are
supported. Included with this core is an industry stan-
dard digital copy protection system, HDCP* (High-
bandwidth Digital Content Protection) used in state-of-
the-art HDTVs. HDCP technologies protect high-value
digital motion pictures, television programs and audio
against unauthorized interception and copying
between a digital set top box or digital video recorder
and a digital TV or PC.
Note:
The Digital Content Protection, LLC requires that the
purchaser of this LogiCORE IP become an HDCP adopter in
order to obtain keys and to complete the HDCP
implementation. See http://www.digital-cp.com
. [Ref 6]
Features
• Source (TX) and Sink (RX) Controllers
• Compliant to VESA DisplayPort Standard v1.1a and
HDCP Specification rev. 1.3.
• Hardware tested for compliance and interoperability
• One or two pixel-wide video interface supporting up to
a 2560x1600 monitor resolution
• 1,2 or 4 lanes at 1.62 or 2.7 Gbps.
• Optional stream de/encryption with HDCP (1.3 High
Definition Content Protection)
• RGB and YCbCr color space, up to 16 bits per color
• Auto lane rate and width negotiation
• I2C over a 1 Mbps AUX channel
LogiCORE IP DisplayPort™ v1.3
DS735 July 23, 2010 Product Specification
LogiCORE IP Facts
Core Specifics
Supported
Device Family
(1)
1. For a complete listing of supported devices, see the release notes
for this core.
Virtex-6, Virtex-5, Spartan-6
Resources Used
I/O
(to pins)
LUTs FFs
Block
RAMs
Sink
12 ~7000 ~4700 4
Source
13 ~7500 ~3200 12
Provided with Core
Documentation
Product Specification
User Guide
Design File
Formats
Verilog and VHDL
NGC Netlist
Scripts for Unix and Windows®
Constraints File
.ucf (user constraints file)
Full Timing Constraints
Transceiver Physical Constraints
Verification Verilog Test Bench
Instantiation
Template
Verilog and VHDL Wrapper
Example Design
Simple RTL Source Policy Maker
Full Netlist Source Policy Maker
RTL Sink Policy Maker
RTL EDID ROM, RTL I2C Controller
Demonstration Test Bench
Design Tool Requirements
Xilinx
Implementation
Tools
ISE®12.2
Verification
Mentor Graphics® ModelSim® 6.5c and
above
Cadence® Incisive Enterprise Simulator
(IES) v9.2 and above
Synopsys® VCS and VCS MX 2009.12 and
above
Simulation Mentor Graphics ModelSim 6.5c and above
Synthesis Xilinx XST
Support
Provided by Xilinx, Inc.
资源评论
- rybird2012-07-27正好要用xilinx的方案,就看到了这个,可惜只是一个简单的介绍性文档。
- hebutwh20122015-08-31了解一下新知识
Fiti99470
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