JEDEC Standard No. 82-17.01
Page 1
DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 1.8-V CONFIGURABLE
REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
(From JEDEC Board Ballot JCB-05-102, formulated under the cognizance of the JC-40 Committee on
Digital Logic.)
1 Scope
This standard defines standard specifications of DC interface parameters, switching parameters, and test
loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for
DDR2 RDIMM applications.
The purpose is to provide a standard for the SSTUA32S868 and SSTUA32D868 (see Note) logic device,
for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of
use.
NOTE The designation SSTUA32S868 and SSTUA32D868 refers to the part designation of a series of commercial
logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters
to make up a complete part designation.
2 Device Standard
2.1 Description
This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V
DD
operation.
All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable
(CSGEN), control (C), and reset (RESET
) inputs, which are LVCMOS. All outputs are edge-controlled
circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain
error (QERR
) output.
The SSTUA32S868 and SSTUA32D868 operates from a differential clock (CK and CK
). Data are
registered at the crossing of CK going high and CK
going low.
The device supports low-power standby operation. When RESET
is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V
REF
) inputs are allowed. In addition,
when RESET
is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS
RESET
and C inputs always must be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET
must be held
in the low state during power up.
In the DDR2 RDIMM application, RESET
is specified to be completely asynchronous with respect to CK
and CK
. Therefore, no timing relationship can be ensured between the two. When entering reset, the
register will be cleared and the data outputs will be driven low quickly, relative to the time to disable the
differential input receivers. However, when coming out of reset, the register will become active quickly,
relative to the time to enable the differential input receivers. As long as the data inputs are low, and the
clock is stable during the time from the low-to-high transition of RESET
until the input receivers are fully
JEDEC
