1 Introduction .....................................................................................................................................................1
1.1 LRDIMM Memory Buffer Overview....................................................................................................................1
1.2 Memory Buffer Functionality .............................................................................................................................1
1.2.1 Memory Buffer Key Features.............................................................................................................................1
1.2.2 DDR SDRAM ....................................................................................................................................................1
1.2.3 Byte Group Signal Mapping ..............................................................................................................................2
1.3 LRDIMM DDR3 Memory Buffer Block Diagram ................................................................................................3
1.4 Interfaces ..........................................................................................................................................................4
1.4.1 HOST Interface .................................................................................................................................................4
1.4.2 DDR3 DRAM Interface......................................................................................................................................4
1.4.3 SMBus Target Interface ....................................................................................................................................4
1.5 References........................................................................................................................................................4
1.6 Glossary ............................................................................................................................................................5
2 Ballout and Package Information ..................................................................................................................7
2.1 588-Ball FBGA (20x38 Array, 25.2x13.5 mm Body Size, 0.65 mm Pitch, MO-301A Variation A) Pin
configuration......................................................................................................................................................7
2.2 Pin Assignments for the LR-DIMM DDR3 Memory Buffer (MB)........................................................................8
2.3 Package Information .......................................................................................................................................16
3 Pin Descriptions............................................................................................................................................17
3.1 Pin Description ................................................................................................................................................17
4 Host Interface Protocol and Requirement ..................................................................................................21
4.1 MB Modes of operation ...................................................................................................................................21
4.1.1 Direct Rank Addressing Mode ........................................................................................................................21
4.1.2 Rank Multiplication Mode ................................................................................................................................22
4.2 Command, Address, and Control Signal usage ..............................................................................................34
4.2.1 Command Signals...........................................................................................................................................34
4.2.2 Address Signals ..............................................................................................................................................35
4.2.3 Control Signals................................................................................................................................................36
4.3 Parity ...............................................................................................................................................................39
4.3.1 Parity Timing Scheme Waveforms..................................................................................................................39
4.4 Dynamic 1T/3T Timing Transaction and Output Inversion Enabling/Disabling ...............................................41
4.5 Control Word Access Mechanism ...................................................................................................................45
4.6 Address Mirroring............................................................................................................................................46
5 DRAM Interface Protocol and Requirement................................................................................................47
5.1 Signals and Usage ..........................................................................................................................................47
5.1.1 Command / Address .......................................................................................................................................47
5.1.2 Control Signals................................................................................................................................................48
5.1.3 Clock Outputs..................................................................................................................................................49
5.1.4 Reset...............................................................................................................................................................50
5.1.5 DRAM data bus...............................................................................................................................................50
5.2 Turnaround Cycles..........................................................................................................................................50
6 Initialization ...................................................................................................................................................51
6.1 Initialization Overview .....................................................................................................................................51
6.2 Power-on Initialization.....................................................................................................................................52
6.2.1 Clock Stabilization Time tSTAB ......................................................................................................................53
6.3 Initialization with Stable Power (Soft Reset) ...................................................................................................55
6.4 Host RCW to Configure MB............................................................................................................................56
6.5 Host MRS to Configure DRAM .......................................................................................................................56
6.6 Host to DRAM ZQ Calibration.........................................................................................................................57
6.7 MB-DRAM Training.........................................................................................................................................57
6.8 Host-MB Training............................................................................................................................................57
7 Electrical, Timing, Power and Thermal.......................................................................................................59
7.1 Electrical DC and AC Parameters ..................................................................................................................59
7.1.1 Absolute maximum ratings .............................................................................................................................59
7.1.2 DC and AC Specifications ..............................................................................................................................60
7.1.3 DC specifications, IDD Specifications.............................................................................................................66
7.1.4 Input/Output Capacitance ...............................................................................................................................67
7.2 AC and DC Input and Output Measurement Levels .......................................................................................68
7.2.1 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) ...........................................68
7.2.2 Slew Rate Definitions for Differential Input Signals ........................................................................................69
-i-
JEDEC Standard No. 82-30.01
LRDIMM: Memory Buffer (MB), Version 1.0
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JEDEC
