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JEDEC JESD82-31A.01
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DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02).pdf
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JEDEC
STANDARD
DDR4 Registering Clock Driver
Definition (DDR4RCD02)
JESD82-31A.01
(Revision of JESD82-31A, August 2019)
JANUARY 2023
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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JEDEC Standard No. 82-31A.01
-i-
DDR4 REGISTERING CLOCK DRIVER DEFINITION (DDR4RCD02)
CONTENTS
1 Scope ...........................................................................................................................................1
2 Device standard..........................................................................................................................2
2.1 Description................................................................................................................................2
2.2 Features and Functions .............................................................................................................2
2.2.1 Direct CS Modes.................................................................................................................................. 3
2.2.2 Quad CS Modes................................................................................................................................... 3
2.2.3 Encoded QuadCS Mode ...................................................................................................................... 3
2.3 Initialization ..............................................................................................................................5
2.3.1 Reset Initialization with Stable Power...................................................................................7
2.4 Parity.........................................................................................................................................8
2.4.1 Parity Timing Scheme Waveforms........................................................................................9
2.5 Data Buffer Control Bus .........................................................................................................13
2.5.1 Control Bus Signals .............................................................................................................13
2.5.2 Control Bus Timing .............................................................................................................14
2.5.3 Control Bus Commands.......................................................................................................14
2.5.4 Command Sequence Descriptions .......................................................................................15
2.6 DQ Bus Termination in LRDIMM application ......................................................................24
2.7 Power saving modes ...............................................................................................................27
2.7.1 Register CKE Power Down .................................................................................................27
2.7.2 Clock Stopped Power Down Mode .....................................................................................33
2.8 Dual Frequency Support .........................................................................................................36
2.8.1 Input Clock Frequency Change ...........................................................................................36
2.9 Output Inversion Enabling/Disabling .....................................................................................38
2.9.1 1T Timing Only ...................................................................................................................42
2.10 ZQ Calibration ......................................................................................................................42
2.11 Latency Equalization Support...............................................................................................43
2.12 Output Delay Control............................................................................................................43
2.13 Output Slew Rate Control.....................................................................................................44
2.14 CA Bus Training Modes .......................................................................................................44
2.15 Transparent Mode .................................................................................................................46
2.16 Control Gear-down Mode (CGM) ........................................................................................46
2.16.1 CKE Power Down Mode in Control Gear-down Mode ....................................................49
2.16.2 Handling of parity errors in Control Gear-down Mode.....................................................49
2.16.3 Output Delay Control Restrictions in Control Gear-down Mode......................................49
2.16.4 Weak Drive Feature in Control Gear-down Mode ............................................................49
2.17 Command to Address Latency (CAL) Mode........................................................................49
2.17.1 Handling of parity errors in CAL Mode ...........................................................................51
2.18 Simultaneous CAL Mode and Control Gear-down Mode ....................................................51
2.18.1 Clock-stopped power down events when CAL+CGM are enabled...................................52
2.19 Optional NVDIMM Support Feature....................................................................................54
2.19.1 NVDIMM Initialization Sequence.....................................................................................54
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