JEDEC Standard No. 82-513
-i-
DDR5 REGISTERING CLOCK DRIVER DEFINITION (DDR5RCD03)
Contents
Page
1 Scope .................................................................................................................................1
2 Mechanical Outline .........................................................................................................2
2.1 Pinout.................................................................................................................................3
2.2 Terminal Functions............................................................................................................4
3 Device Standard...............................................................................................................6
3.1 Description ........................................................................................................................6
3.2 Logic Diagram Positive Logic...........................................................................................7
3.3 Register Operation.............................................................................................................8
3.3.1 Chip Select Operation........................................................................................................8
3.3.2 ODT Operation..................................................................................................................8
3.3.3 QCA Bus Operation ..........................................................................................................9
3.3.4 QCS Operation ................................................................................................................10
3.3.5 Output Inversion and Mirroring ......................................................................................10
3.3.6 ZQ Calibration.................................................................................................................10
3.3.7 Latency Equalization Support .........................................................................................11
3.3.8 Per-group Output Delay Control .....................................................................................11
3.3.9 Per-bit QCA Output Delay Control.................................................................................12
3.3.10 Power Down Operation ...................................................................................................12
3.3.11 VHost Mode ....................................................................................................................12
3.3.12 Transparent Mode............................................................................................................13
3.3.13 CA Validation Pass-Through Mode ................................................................................13
3.3.14 DRAM Interface and Data Buffer Interface Training Support .......................................14
3.4 Command Address Bus ...................................................................................................14
3.4.1 Double Data Rate DCA...................................................................................................15
3.4.2 Single Data Rate DCA.....................................................................................................18
3.4.3 SDR to DDR Transition ..................................................................................................19
3.5 Parity................................................................................................................................19
3.5.1 Single UI DRAM Commands with Parity Enabled.........................................................20
3.5.2 2UI DRAM Commands with Parity Enabled..................................................................21
3.5.3 ALERT_n Assertion........................................................................................................24
3.6 DCA Decision Feedback Equalization............................................................................25
3.6.1 DFE Tap Configurations .................................................................................................26
3.6.2 DFE Gain and Tap Range................................................................................................26
3.6.3 DCA DFE Tap Measurement ..........................................................................................27
3.7 Continuous Time Linear Equalization (CTLE)...............................................................29
3.7.1 Background......................................................................................................................29
3.7.2 CTLE Transfer Function .................................................................................................29
3.8 RX Loopback...................................................................................................................33
3.8.1 Loopback Mode...............................................................................................................33
3.8.2 Loopback Ports................................................................................................................33
3.8.3 Pin Assignment for Loopback, Timing Diagrams, and Timing Parameters ...................34
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