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JEDEC JESD82-27.01-2023
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Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications.pdf
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JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD82-27.01
March 2023
JEDEC
STANDARD
Definition of the SSTUB32869 Registered
Applications
Buffer with Parity for DDR2 RDIMM
(Editorial Revision of JESD82-27 May 2007)
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JEDEC
JEDEC Standard No. 82-27.01
-i-
Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM
Applications
Contents
Page
1 Scope ................................................................................................................................................... 1
2 Device Standard .................................................................................................................................. 1
2.1 Description .......................................................................................................................................... 1
2.2 150-ball TFBGA (MO-246xx) ........................................................................................................... 3
2.3 Pinout Top View for 150-ball TFBGA ............................................................................................... 4
2.4 Terminal Functions ............................................................................................................................. 5
2.5 Function Table ................................................................................................................................... 6
2.6 Logic Diagram ................................................................................................................................... 9
2.7 Register Timing ............................................................................................................................... 10
2.8 Absolute Maximum Ratings ............................................................................................................ 17
2.9 Recommended Operating Conditions .............................................................................................. 18
2.10 DC Specifications ............................................................................................................................ 19
2.11 Timing Requirements ...................................................................................................................... 20
2.12 AC Specifications ............................................................................................................................ 21
2.13 Output Buffer Characteristics .......................................................................................................... 21
3 Test Circuits And Switching Waveforms ........................................................................................ 22
3.1 Parameter Measurement Information (VDD = 1.7V .. 1.9V) .......................................................... 22
3.2 Output Slew Rate Measurement Information (VDD = 1.7V .. 1.9V) .............................................. 24
3.3 Error Output Load Circuit and Voltage Measurement Information (VDD = 1.7V .. 1.9V) ............ 25
3.4 Error Output Load Circuit and Voltage Measurement Information (VDD = 1.7V .. 1.9V) ............ 26
4 Reference to Other Applicable JEDEC Standards and Publications ............................................... 28
Annex A — (Informative) Differences between JESD82-27.01 and JESD82-27 ...................................... 28
List of Tables
Table 1 — Terminal Functions ..................................................................................................................... 5
Table 2 — Function Table (each Flip Flop) ................................................................................................. 6
Table 3 — Parity and Standby Function Table ............................................................................................ 7
Table 4 — Parity Error Detect in Low-power Mode
1
.................................................................................. 8
Table 5 — Absolute Maximum Ratings over Operating Free-air Temperature Range
1
................................17
Table 6 — Mode Select .............................................................................................................................. 17
Table 7 — Recommended Operating Conditions (see NOTE 1) ............................................................... 18
Table 8 — Electrical Characteristics over Recommended Operating Free-air Temperature Range .......... 19
Table 9 — Capacitance Values for SSTUB32869 ..................................................................................... 19
Table 10 — Timing Requirements over Recommended Operating Free-air Temperature Range
(see Figure 6) .......................................................................................................................... 20
Table 11 — Switching Characteristics over Recommended Operating Free-air Temperature Range
(Unless Otherwise Noted) (see section 3.1) ........................................................................... 21
Table 12 — Output Edge Rates over Recommended Operating Free-air Temperature Range
(see section 3.2) ...................................................................................................................... 21
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