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June 2021
JEDEC
STANDARD
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
Low Power Double Data Rate 5
(LPDDR5)
JESD209-5B
(Revision of JESD209-5A, January 2020)
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
publication may be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated
in the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or refer to www.jedec.org
under Standards and Documents for alternative contact information.
Published by
©JEDEC Solid State Technology Association 2021
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107
This document may be downloaded free of charge; however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
charge for or resell the resulting material.
PRICE: Contact JEDEC
Printed in the U.S.A.
All rights reserved
JEDEC Standard No. 209-5B
i
Contents
1 Scope ........................................................................................................................ 1
2 Overview ................................................................................................................... 1
2.1 Features .................................................................................................................... 1
2.2 Functional Description ............................................................................................... 1
2.2.1 Pad Definition and Description .................................................................................. 3
2.2.2 Pin per byte ............................................................................................................... 4
2.2.3 LPDDR5/LPDDR5X Bank Architecture ...................................................................... 4
2.2.3.1 Block diagram of bank configuration and Read operation outline .............................. 5
2.2.3.1.1 4Banks / 4Bank Groups Configuration ...................................................................... 5
2.2.3.1.2 8Banks Mode Configuration (Does not apply to LPDDR5X SDRAM) ........................ 6
2.2.3.1.3 16Banks Mode Configuration .................................................................................... 7
2.2.3.2 LPDDR5/LPDDR5X Address Translation Table ......................................................... 8
2.2.3.3 Bank architecture transition ....................................................................................... 8
2.2.3.4 Burst Operation ......................................................................................................... 8
2.2.4 LPDDR5 SDRAM Addressing ...................................................................................14
2.2.5 Speed Grade ............................................................................................................20
2.2.6 Burst Sequence........................................................................................................22
3 WCK Clocking ..........................................................................................................23
4 Initialization and Training ..........................................................................................26
4.1 Power-up, Initialization and Power-off Procedure .....................................................26
4.1.1 Voltage Ramp and Device Initialization ....................................................................26
4.1.2 Dual VDD2 Rail setting (MR13 OP[7]) and its change ..............................................30
4.1.3 Reset Initialization with Stable Power .......................................................................31
4.1.4 Power-off Sequence .................................................................................................31
4.1.5 Uncontrolled Power-off Sequence ............................................................................31
4.2 Training ....................................................................................................................32
4.2.1 ZQ Calibration ..........................................................................................................32
4.2.1.1 Calibration During Powerup and Initialization ...........................................................32
4.2.1.1.1 Background Calibration ............................................................................................33
4.2.1.1.2 Latching ZQ Calibration Results in Background Calibration Mode ............................34
4.2.1.1.3 Command-Based Calibration ...................................................................................34
4.2.1.1.4 Latching ZQ Calibration Results in Command-Based Calibration Mode ...................35
4.2.1.1.5 Maintaining Accurate Calibration - Background Calibration Mode ............................35
4.2.1.1.6 Maintaining Accurate Calibration – Command-Based Calibration Mode ...................36
4.2.1.1.7 Changing between Calibration Modes ......................................................................36
4.2.1.1.7.1 Changing between Calibration Modes when DVFSQ is not active ............................36
4.2.1.1.7.2 Changing between Calibration Modes when DVFSQ is active ..................................37
4.2.1.2 ZQ Stop Functionality ...............................................................................................38
4.2.1.2.1 ZQ Resistor Sharing by Other Device(s) ..................................................................38
4.2.1.2.1.1 ZQ Resistor Sharing in Background Calibration Mode .............................................38
4.2.1.2.1.2 ZQ Resistor Sharing in Command-Based Calibration Mode .....................................
38
4
.2.1.2.2 Stopping Background Calibration when DVFSQ is active .........................................38
4.2.1.2.3 Stopping Background Calibration when VDDQ is Powered Off ................................39
4.2.1.3 ZQ Reset..................................................................................................................40
4.2.1.4 Multi-die Package Considerations ............................................................................40
4.2.1.4.1 Other Considerations in Background Calibration Mode ............................................41
4.2.1.4.2 Other Considerations in Command-Based Calibration Mode ...................................41
4.2.1.5 ZQ External Resistor, Tolerance, and Capacitive Loading ........................................41
4.2.1.6 Flow Chart Examples ...............................................................................................41
4.2.2 Command Bus Training ............................................................................................47
4.2.2.1 Three physical Mode Register ..................................................................................47
4.2.2.2 Command Bus Training Mode1 ................................................................................48
JEDEC Standard No. 209-5B
ii
4.2.2.3 Command Bus Training Mode1 (FSP with DVFSQ enable) ......................................56
4.2.2.4 Command Bus Training Mode2 ................................................................................61
4.2.2.5 Command Bus Training Mode2 (FSP with DVFSQ enable) ......................................71
4.2.3 CA VREF Training ....................................................................................................76
4.2.4 DQ VREF Training ...................................................................................................76
4.2.5 WCK2CK Leveling ...................................................................................................76
4.2.5.1 WCK2CK Leveling Mode (write-leveling called in LPDDR4) .....................................76
4.2.5.2 WCK2CK Leveling Procedure and Related AC parameters ......................................77
4.2.6 Duty Cycle Adjuster (DCA) .......................................................................................80
4.2.6.1 Duty Cycle Adjuster Range ......................................................................................81
4.2.6.2 Relationship between WCK waveform and DCA Code Change ................................82
4.2.6.3 The relationship between DCA Code Change and DQ output/RDQS timing .............83
4.2.7 Read DCA (Duty Cycle Adjuster) ..............................................................................84
4.2.7.1 Read Duty Cycle Adjuster Range .............................................................................84
4.2.7.2 The relationship between Read DCA Code Change and DQ output/RDQS timing ...84
4.2.8 Duty Cycle Monitor (DCM) .......................................................................................85
4.2.8.1 DCM Functional Description .....................................................................................85
4.2.8.2 DCM Sequence ........................................................................................................86
4.2.9 READ DQ Calibration ...............................................................................................88
4.2.9.1 READ DQ Calibration Training Procedure ................................................................88
4.2.9.2 READ DQ Calibration Example ................................................................................92
4.2.9.3 READ DQ Calibration after Power Down Exit ...........................................................93
4.2.9.4 DMI Behavior Control for RDC .................................................................................94
4.2.9.4.1.1 DMI Output Behavior Mode 1 ...................................................................................94
4.2.9.4.1.2 DMI Output Behavior Mode 2 ...................................................................................94
4.2.10 WCK-DQ Training ....................................................................................................95
4.2.10.1 Training procedure ...................................................................................................96
4.2.10.1.1 Relationship between MR setting and FIFO training behavior ..................................97
4.2.10.1.1.1 DMI Output Behavior Mode 1 .............................................................................99
4.2.10.1.1.2 DMI Output Behavior Mode 2 .............................................................................99
4.2.10.2 WCK-RDQS_t/Parity Training ................................................................................. 100
4.2.10.3 FIFO Pointer Reset and Synchronism .................................................................... 100
4.2.10.4 Command constraints for Write/Read FIFO command ........................................... 105
4.2.11 RDQS toggle mode ................................................................................................ 107
4.2.12 Enhanced RDQS training mode ............................................................................. 110
4.2.13 Read/Write-based WCK-RDQS_t Training ............................................................. 114
4.2.13.1 Relationship between MR setting and Read/Write-based WCK-RDQS_t Training
behavior ........................................................................................................... 115
4.2.14 Rx Offset Calibration Training ................................................................................. 117
4.2.14.1 Offset Calibration Training Description ................................................................... 117
4.2.14.2 Offset Calibration Training Sequence ..................................................................... 117
5 Simplified LPDDR5 State Diagram
................................
......................................... 118
6 Mode Register Definition ........................................................................................ 123
6.1 Mode Register Assignment and Definition in LPDDR5 SDRAM .............................. 123
6.2 Mode Register Assignment and Definition in LPDDR5X SDRAM ........................... 126
6.3 Mode Register Definition ........................................................................................ 130
6.3.1 Mode Register definition ......................................................................................... 130
7 Operating ............................................................................................................... 188
7.1 Truth Table ............................................................................................................. 188
7.1.1 Command Truth Table ............................................................................................ 188
7.2 WCK Operation ...................................................................................................... 191
7.2.1 WCK2CK Synchronization operation ...................................................................... 191
7.2.1.1 WCK2CK Synchronization ..................................................................................... 191
JEDEC Standard No. 209-5B
iii
7.2.1.2 CAS Command with WCK2CK Synchronization Bits .............................................. 192
7.2.1.3 WCK2CK Sync operation followed by a WRITE command ..................................... 194
7.2.1.4 WCK2CK Sync operation followed by a READ command ...................................... 197
7.2.1.5 WCK2CK Sync operation with CAS(WS_FS=1) ..................................................... 200
7.2.1.6 Rank to rank WCK2CK Sync operation .................................................................. 203
7.2.2 WCK2CK SYNC Off Timing Definition .................................................................... 207
7.2.3 Write Clock Always on mode (WCK Always on mode) ............................................ 217
7.3 Row operation ........................................................................................................ 222
7.3.1 Active Command .................................................................................................... 222
7.3.1.1 8-Bank mode SDRAM Operation ........................................................................... 224
7.3.1.2 BG mode SDRAM Operation.................................................................................. 224
7.3.2 Pre-Charge Operation ............................................................................................ 225
7.3.2.1 Pre-Charge Operation ............................................................................................ 225
7.3.2.2 Auto-Precharge Operation ..................................................................................... 229
7.3.2.2.1 Delay time from Write to Read with Auto Precharge ............................................... 231
7.3.2.2.2 Burst Read with Auto-Precharge ............................................................................ 232
7.3.2.2.3 Burst Write with Auto-Precharge............................................................................. 233
7.4 Read/Write Operation ............................................................................................. 234
7.4.1 Read and Write Access Operations ........................................................................ 234
7.4.2 Read Preamble and Postamble .............................................................................. 234
7.4.3 Burst Read Operation ............................................................................................ 235
7.4.3.1 Read Timing ........................................................................................................... 235
7.4.3.2 Read to Read Operation without additional WCK2CK-sync .................................... 237
7.4.3.3 Read to Read Operation with additional WCK2CK-sync ......................................... 239
7.4.3.4 Read operation followed by write operation ............................................................ 240
7.4.4 READ Burst end to PRECHARGE Delay (tRBTP) .................................................. 242
7.4.5 RDQS Mode ........................................................................................................... 244
7.4.5.1 RDQS Timing ......................................................................................................... 244
7.4.5.2 RDQS Related Functionalities ................................................................................ 245
7.4.5.3 Mode Registers for RDQS ...................................................................................... 247
7.4.5.4 RDQS Pattern Definition ........................................................................................ 248
7.4.6 Write Preamble and Postamble .............................................................................. 250
7.4.7 Burst Write Operation ............................................................................................. 251
7.4.7.1 Write Timing ........................................................................................................... 251
7.4.7.2 Write to Write Operation without additional WCK2CK-sync .................................... 252
7.4.7.3 Write to Write Operation with additional WCK2CK-sync ......................................... 254
7.4.7.4 Write operation followed by read operation ............................................................ 255
7.4.8 Read and Write Latency ......................................................................................... 256
7.4.8.1 Read and Read
-to-P
recharge Latencies ................................................................ 256
7.4.8.2 Write Latency ......................................................................................................... 258
7.4.8.3 Write Recovery time ............................................................................................... 260
7.4.9 Masked Write ......................................................................................................... 262
7.4.10 Data Mask (DM) and Data Bus Inversion (DBI-DC) Function ................................. 266
7.4.10.1 DMI Pin Behavior with Write Related Commands ................................................... 267
7.4.10.2 DMI Pin Behavior with Read and MRR Command ................................................. 269
7.4.10.3 DMI Pin Behavior with Read FIFO and Read DQ Calibration Commands .............. 269
7.5 Refresh operation ................................................................................................... 271
7.5.1 Refresh command .................................................................................................. 271
7.5.2 Refresh Requirement ............................................................................................. 280
7.5.3 Optimized Refresh ................................................................................................. 281
7.5.4 Self Refresh Operation ........................................................................................... 283
7.5.4.1 Power Down Entry and Exit during Self refresh ...................................................... 285
7.5.4.2 Command input Timing after Power Down Exit during Self Refresh ....................... 287
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