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JEDEC
STANDARD
Low Power Double Data Rate 5
(LPDDR5)
JESD209-5
FEBRUARY 2019
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and approved
through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC
legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the
proper product for use by those other than JEDEC members, whether the standard is to be used either
domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption may
involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to
any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or
publications.
The information included in JEDEC standards and publications represents a sound approach to product
specification and application, principally from the solid state device manufacturer viewpoint. Within the
JEDEC organization there are procedures whereby a JEDEC standard or publication may be further
processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in the
standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should
be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents
for alternative contact information.
Published by
©JEDEC Solid State Technology Association 2019
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2108
JEDEC retains the copyright on this material. By downloading this file the individual agrees not to
charge for or resell the resulting material.
PRICE: Contact JEDEC
Printed in the U.S.A.
All rights reserved
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PLEASE!
DON’T VIOLATE
THE
LAW!
This document is copyrighted by JEDEC and may not be
reproduced without permission.
For information, contact:
JEDEC Solid State Technology Association
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107
or refer to www.jedec.org under Standards-Documents/Copyright Information.
Downloaded by kui sun (kui.sun@unisoc.com) on Feb 19, 2019, 10:55 pm PST
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Downloaded by kui sun (kui.sun@unisoc.com) on Feb 19, 2019, 10:55 pm PST
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JEDEC Standard No. 209-5
-i-
Contents
1 Scope......................................................................................................................................... 1
2 Overview ................................................................................................................................... 2
2.1 Features ..................................................................................................................... 2
2.2 Functional Description .................................................................................................. 2
2.2.1 Pad Definition and Description ...................................................................................... 2
2.2.2 Pin per byte ................................................................................................................ 3
2.2.3 LPDDR5 Bank Architecture ........................................................................................... 4
2.2.3.1 Block diagram of bank configuration and Read operation outline ....................................... 5
2.2.3.1.1 4 Bank / 4 Bank Groups Configuration ............................................................................ 5
2.2.3.1.2 8 Bank Mode Configuration ........................................................................................... 6
2.2.3.1.3 16 Bank Mode Configuration ......................................................................................... 7
2.2.3.2 Address mapping ......................................................................................................... 7
2.2.3.3 Bank architecture transition ........................................................................................... 7
2.2.3.4 Burst Operation ........................................................................................................... 7
2.2.4 LPDDR5 SDRAM Addressing .......................................................................................13
2.2.5 Speed Grades ............................................................................................................19
2.2.6 Burst Sequence ..........................................................................................................20
3 WCK Clocking...........................................................................................................21
4 Initialization and Training ..........................................................................................24
4.1 Power-up, Initialization and Power-off Procedure ............................................................24
4.1.1 Voltage Ramp and Device Initialization ..........................................................................24
4.1.2 Reset Initialization with Stable Power ............................................................................28
4.1.3 Power-off Sequence ....................................................................................................28
4.1.4 Uncontrolled Power-off Sequence .................................................................................28
4.2 Training .....................................................................................................................29
4.2.1 ZQ Calibration ............................................................................................................29
4.2.1.1 Calibration .................................................................................................................29
4.2.1.1.1 Calibration During Powerup and Initialization..................................................................29
4.2.1.1.2 Background Calibration ...............................................................................................29
4.2.1.1.3 Latching ZQ Calibration Results in Background Calibration Mode .....................................30
4.2.1.1.4 Command-Based Calibration .......................................................................................31
4.2.1.1.5 Latching ZQ Calibration Results in Command-Based Calibration Mode .............................31
4.2.1.1.6 Maintaining Accurate Calibration - Background Calibration Mode ......................................32
4.2.1.1.7 Maintaining Accurate Calibration - Command-Based Calibration Mode ..............................32
4.2.1.1.8 Changing between Calibration Modes ...........................................................................33
4.2.1.1.8.1 Changing between Calibration Modes when DVFSQ is not active .....................................33
4.2.1.1.8.2 Changing between Calibration Modes when DVFSQ is active ..........................................34
4.2.1.2 ZQ Stop Functionality ..................................................................................................35
4.2.1.2.1 ZQ Resistor Sharing by Another Device(s) .....................................................................35
4.2.1.2.1.1 ZQ Resistor Sharing in Background Calibration Mode .....................................................35
4.2.1.2.1.2 ZQ Resistor Sharing in Command-Based Calibration Mode .............................................35
4.2.1.2.2 Stopping Background Calibration when DVFSQ is active .................................................35
4.2.1.2.3 Stopping Background Calibration when VDDQ is Powered Off .........................................36
4.2.1.3 ZQ Reset ...................................................................................................................37
4.2.1.4 Multi-die Package Considerations .................................................................................38
4.2.1.4.1 Other Considerations in Background Calibration Mode ....................................................38
4.2.1.5 Other Considerations in Command-Based Calibration Mode ............................................38
4.2.1.6 ZQ External Resistor, Tolerance, and Capacitive Loading ................................................38
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