COMMITTEE LETTER BALLOT
Solid State Technology Association
3103 North 10th Street
Arlington, Virginia 22201
TEL: (703) 907-7560
Ballot Template Version draft rev. 8/11
© JEDEC 2011
Committee: JC42.3
Committee Item Number: xxxx.yy
Subject: DDR5 Full Spec Draft Rev0.1
Background: All red and black items are for ballot, red text identifies the updates from the
previous ballot. Items in grey are not part of the ballot material and are for
reference only
Keywords: DDR5, Full Specification
DDR5 Proposal Item 1845.31A
Page 2 of 2
P R O P O S E D
REVISION HISTORY
Revision Author Date Status and Description
Rev0.1 C.Cox 12/5/17 Initial Format Rev0.1 - Includes all ballots through Q3’17
Document Formating Legend
Colors used in this Document and what they mean:
RED - All Red text is defined as somethin
g that is NEW
BLACK - Is considered the standard or the current Ballot.
LIGHT GREY - All
Light Grey text is defined as something that should be considered TBD. The content may be accurate or the same
as previous technologies but has not yet been reviewed or determined to be the working assumption.
Special NOTE: Some legacy diagrams t
hat have not been updated may be BLACK or RED but that does not indicate that they are
new or current working assumption. In the case where there is a digram that is BLACK or RED, it is important to look at the section for
reference. If the section/heading is BLACK or RED, then it is as intended. If the section/heading is GREY, then assume its only an
artifact of the old diagram that could not easily be changed.
Proposed DDR5 Full spec (79-5) Item No. xxxx.yyy
Page 1
1. Scope ................................................................................................................................................................................... 1
2. DDR5 SDRAM Package, Pinout Description and Addressing ............................................................................................. 2
2.1 DDR5 SDRAM Row for X4, X8 - Q3’17 Ballot#1830.69B ............................................................................................... 2
2.2 DDR5 SDRAM Ball Pitch - Q3’17 Ballot#1830.69B ........................................................................................................ 2
2.3 DDR5 SDRAM Columns for X4, X8 - Q3’17 Ballot#1830.69B ........................................................................................ 2
2.4 DDR5 SDRAM X4/8 Ballout using MO-xxx - Q3’17 Ballot #1830.69B ............................................................................ 3
2.5 DDR5 SDRAM X16 Ballout using MO-xxx - No Ballot .................................................................................................... 4
2.6 Pinout Description - Q4’16 Ballot #1830.69 .................................................................................................................... 5
2.7 DDR5 SDRAM Addressing - Q2’17 Item#1830.36B ....................................................................................................... 7
3. Functional Description.......................................................................................................................................................... 8
3.1 Simplified State Diagram - No Ballot ............................................................................................................................... 8
3.2 Basic Functionality - No Ballot......................................................................................................................................... 9
3.3 RESET and Initialization Procedure - Q1’17 Ballot ......................................................................................................... 10
3.3.1 Power-up Initialization Sequence ....................................................................................................................... 10
3.3.2 TBD - VDD Slew rate at Power-up Initialization Sequence ................................................................................ 13
3.3.3 TBD - Reset Initialization with Stable Power ...................................................................................................... 14
3.4 Mode Register Definition - Q1’17 Ballot #1845.17 .......................................................................................................... 15
3.4.1 Mode Register Read (MRR) ............................................................................................................................... 15
3.4.2 Mode Register WRITE (MRW) ........................................................................................................................... 16
3.4.3 Mode Register Truth Tables and Timing Constraints ......................................................................................... 16
3.5 Mode Registers - Q1’17 Ballot #1845.17 (OUT OF DATE) ............................................................................................. 20
3.5.1 Mode Register Assignment and Definition in DDR5 SDRAM............................................................................ 20
3.5.2 MR0 (MA[7:0]=00H) - Q3’17 Ballot #1845.35B .................................................................................................. 22
3.5.3 MR1 (MA [7:0] = 01H) - PDA Mode Details - Q3’17 Ballot #1845.35B............................................................... 23
3.5.4 MR2 (MA [7:0] = 02H) - DQS Training - Q3’17 Ballot #1845.35B ...................................................................... 24
3.5.5 MR3 (MA[7:0]=03H) - Functional Modes - Q3’17 Ballot #1845.33B................................................................... 25
3.5.6 MR4 (MA[7:0]=04H) - Refresh Settings - Q1’17 Ballot #1845.32B w/Editorial update ....................................... 26
3.5.7 MR5 (MA[7:0]=05H) - IO Settings - Q2’17 Ballot #1845.31A ............................................................................. 27
3.5.8 MR6 (MA[7:0]=06H) - Write Recovery Time & tRTP - Q2’17 Ballot #1845.31A ................................................. 28
3.5.9 MR7 (MA[7:0]=07H) - Q2’17 Ballot #1845.31A .................................................................................................. 29
3.5.10 MR8 (MA[7:0]=08H) - Preamble / Postamble - Q2’17 Ballot #1845.31A.......................................................... 30
3.5.11 MR9 (MA[7:0]=09H) - VREF Config - Q2’17 Ballot #1845.30A - w/Editorial Updates ...................................... 31
3.5.12 MR10 (MA[7:0]=0AH) - Vref DQ Calibration Settings - Q2’17 Ballot #1845.30A..............................................32
3.5.13 MR11 (MA[7:0]=0BH) - Vref CA Calibration Settings - Q2’17 Ballot #1845.30A ..............................................32
3.5.14 MR12 (MA [7:0] = 0CH) - tCCD_L - No Ballot .................................................................................................. 33
3.5.15 MR13 (MA [7:0] = 0CH) - Blank - No Ballot ...................................................................................................... 34
3.5.16 MR14 (MA[7:0]=0EH) - ECC Configuration - Q1’17 Ballot #1845.40 ............................................................... 35
3.5.17 MR15 (MA[7:0]=0FH) - ECS Threshold - Q1’17 Ballot #1845.40 ..................................................................... 35
3.5.18 MR16 (MA [7:0] = 10H) - Reserved for Transparency 1 - Q1’17 Ballot #1845.40 ............................................ 36
3.5.19 MR17 (MA [7:0] = 11H) - Reserved for Transparency 2 - Q1’17 Ballot #1845.40 ............................................ 36
3.5.20 MR18 (MA [7:0] = 12H) - Reserved for Transparency 3 - Q1’17 Ballot #1845.40 ............................................ 36
3.5.21 MR19 (MA [7:0] = 13H) - Reserved for Transparency 4 - Q1’17 Ballot #1845.40 ............................................ 36
3.5.22 MR20 (MA [7:0] = 14H) - Reserved for Transparency 5 - Q1’17 Ballot #1845.40 ............................................ 37
3.5.23 MR21 (MA [7:0] = 15H) - Reserved for Transparency 6 - Q1’17 Ballot #1845.40 ............................................ 37
3.5.24 MR22 (MA [7:0] = 16H) - Reserved for Transparency 7 - Q1’17 Ballot #1845.40 ............................................ 37
3.5.25 MR23 (MA [7:0] = 17H) - PPR Settings - Q1’17 Ballot #1845.41 ..................................................................... 38
3.5.26 MR24 (MA [7:0] = 18H) - Blank - No Ballot....................................................................................................... 39
3.5.27 MR25 (MA[7:0]=19H) - Read Training Mode Settings - Q1’17 Ballot #1845.42 ............................................... 40
3.5.28 MR26 (MA[7:0]=1AH) - Read Pattern Data0 / LFSR0 - Q1’17 Ballot #1845.42 ............................................... 41
3.5.29 MR27 (MA[7:0]=1BH) - Read Pattern Data1 / LFSR1 - Q1’17 Ballot #1845.42 ............................................... 41
3.5.30 MR28 (MA[7:0]=1CH) - Read Pattern Invert DQL7:0 (DQ7:0) - Q1’17 Ballot #1845.42................................... 42
3.5.31 MR29 (MA[7:0]= DH) - Read Pattern Invert DQU7:0 (DQ15:8) - Q1’17 Ballot #1845.42 ................................. 42
3.5.32 MR30 (MA[7:0]=1EH) - Read LFSR Assignments - Q1’17 Ballot #1845.42..................................................... 43
3.5.33 MR31 (MA[7:0]=1FH) - Read Training Pattern Address - Q1’17 Ballot #1845.42 ............................................ 43
3.5.34 MR32 (MA[7:0]=20H) - CK ODT - Q2’17 Ballot #1845.43 ....................................................................
............ 44
3.5.35 MR33 (MA[7:0]=21H) - CA, CS ODT - Q2’17 Ballot #1845.43 w/Editorial Update........................................... 45
3.5.36 MR34 (MA[7:0]=22H) - RTT_PARK & RTT_WR - Q2’17 Ballot #1845.43 ....................................................... 46
3.5.37 MR35 (MA[7:0]=23H) - RTT_NOM_WR & RTT_NOM_RD - Q2’17 Ballot #1845.43 ....................................... 47
3.5.38 MR36 (MA[7:0]= 24H) - ODTL Write Control - Q2’17 Ballot #1845.43 ............................................................. 48
3.5.39 MR37 (MA[7:0]=25H) - ODTL NT Write Control - Q2’17 Ballot #1845.43 ........................................................ 49
3.5.40 MR38 (MA[7:0]=26H) - ODTL Read Control - Q2’17 Ballot #1845.43.............................................................. 50
3.5.41 MR39 (MA[7:0]=27H) - ODTL NT Read Control - Q2’17 Ballot #1845.43 ........................................................ 51
3.5.42 MR40 (MA[7:0]=28H) - ODTL DQS Write Control - Q2’17 Ballot #1845.43 .....................................................52
3.5.43 MR41 (MA[7:0]=29H) - ODTL DQS NT Write Control - Q2’17 Ballot #1845.43 ............................................... 53
3.5.44 MR42 (MA[7:0]=2AH) - ODTL DQS Read Control - Q2’17 Ballot #1845.43..................................................... 54
3.5.45 MR43 (MA[7:0]=2BH) - ODTL NT Read Control - Q2’17 Ballot #1845.43........................................................ 55
3.5.46 MR44 (MA[7:0]=2CH) - Read DQS Offset Timing - Q3’17 Ballot #1845.52 w/Edits......................................... 56
3.5.47 MR45 (MA[7:0]=2DH) - DQS Interval Control - Q3’17 Ballot #1845.44A ......................................................... 57
3.5.48 MR46 (MA[7:0]=2EH) - DQS Osc Count - LSB - Q2’17 Ballot #1845.44 ......................................................... 58
Proposed DDR5 Full spec (79-5) Item No. xxxx.yyy
Page 2
3.5.49 MR47 (MA[7:0]=2FH) - DQS Osc Count - MSB - Q2’17 Ballot #1845.44......................................................... 58
3.5.50 MR48 (MA[7:0]=30H) - Write Pattern Mode - Q2’17 Ballot #1845.45............................................................... 59
3.5.51 MR49 (MA[7:0]=31H) - Fast Zero Init - Q2’17 Ballot #1845.46 ........................................................................ 60
3.5.52 MR50 (MA[7:0]=32H) - Write CRC Settings - Q2’17 Ballot #1845.47 .............................................................. 61
3.5.53 MR51 (MA[7:0]=33H) - Write CRC Auto-Disable Threshold - Q2’17 Ballot #1845.47...................................... 62
3.5.54 MR52 (MA[7:0]=34H) - Write CRC Auto-Disable Window - Q2’17 Ballot #1845.47 ......................................... 63
3.5.55 MR53 (MA[7:0]=35H) - Loopback - Q3’17 Ballot #1845.61 .............................................................................. 64
3.5.56 MR54 to MR62 - Blank - No Ballot.................................................................................................................... 65
3.5.57 MR63 (MA[7:0]=3FH) - DRAM Scratch Pad - Q2’17 Ballot #1845.48 .............................................................. 66
3.5.57.1 RCD Control Word Usage Example........................................................................................................ 66
3.5.58 MR64 to MR111 - Blank - No Ballot.................................................................................................................. 67
3.5.59 Mode Register Definitions for DFE - Q3’17 Ballot #1845.62 w/Editorial Updates ............................................ 68
3.5.60 MR112 (MA[7:0]=70H) - DML DFE VGA - Q3’17 Ballot #1845.62 ................................................................... 69
3.5.61 MR113 (MA[7:0]=71H) - DML DFE Tap-1 - Q3’17 Ballot #1845.62 ................................................................. 70
3.5.62 MR114 (MA[7:0]=72H) - DML DFE Tap-2 - Q3’17 Ballot #1845.62 ................................................................. 71
3.5.63 MR115 (MA[7:0]=73H) - DML DFE Tap-3 - Q3’17 Ballot #1845.62 ................................................................. 72
3.5.64 MR116 (MA[7:0]=74H) - DML DFE Tap-4 - Q3’17 Ballot #1845.62 ................................................................. 73
3.5.65 MR117 through MR119 are undefined. ............................................................................................................ 73
3.5.66 MR120 (MA[7:0]=78H) - DMU DFE VGA - Q3’17 Ballot #1845.62................................................................... 74
3.5.67 MR121 (MA[7:0]=79H) - DMU DFE Tap-1 - Q3’17 Ballot #1845.62................................................................. 75
3.5.68 MR122 (MA[7:0]=7AH) - DMU DFE Tap-2 - Q3’17 Ballot #1845.62 ................................................................ 76
3.5.69 MR123 (MA[7:0]=7BH) - DMU DFE Tap-3 - Q3’17 Ballot #1845.62 ................................................................ 77
3.5.70 MR124 (MA[7:0]=7CH) - DMU DFE Tap-4 - Q3’17 Ballot #1845.62 ................................................................ 78
3.5.71 MR125 through MR127 are undefined. ............................................................................................................ 78
3.5.72 MR128 (MA[7:0]=80H) - DQL0 DFE VGA - Q3’17 Ballot #1845.62 ................................................................. 79
3.5.73 MR129 (MA[7:0]=81H) - DQL0 DFE Tap-1 - Q3’17 Ballot #1845.62................................................................ 80
3.5.74 MR130 (MA[7:0]=82H) - DQL0 DFE Tap-2 - Q3’17 Ballot #1845.62................................................................ 81
3.5.75 MR131 (MA[7:0]=83H) - DQL0 DFE Tap-3 - Q3’17 Ballot #1845.62................................................................ 82
3.5.76 MR132 (MA[7:0]=84H) - DQL0 DFE Tap-4 - Q3’17 Ballot #1845.62................................................................ 83
3.5.77 MR133 through MR135 are undefined. ............................................................................................................ 83
3.5.78 MR136 (MA[7:0]=88H) - DQL1 DFE VGA - Q3’17 Ballot #1845.62 ................................................................. 84
3.5.79 MR137 (MA[7:0]=89H) - DQL1 DFE Tap-1- Q3’17 Ballot #1845.62................................................................. 85
3.5.80 MR138 (MA[7:0]=8AH) - DQL1 DFE Tap-2 - Q3’17 Ballot #1845.62 ............................................................... 86
3.5.81 MR139 (MA[7:0]=8BH) - DQL1 DFE Tap-3 - Q3’17 Ballot #1845.62 ...........................................................
.... 87
3.5.82 MR140 (MA[7:0]=8CH) - DQL1 DFE Tap-4 - Q3’17 Ballot #1845.62 ............................................................... 88
3.5.83 MR141 through MR143 are undefined. ............................................................................................................ 88
3.5.84 MR144 (MA[7:0]=90H) - DQL2 DFE VGA - Q3’17 Ballot #1845.62 ................................................................. 89
3.5.85 MR145 (MA[7:0]=91H) - DQL2 DFE Tap-1 - Q3’17 Ballot #1845.62................................................................ 90
3.5.86 MR146 (MA[7:0]=92H) - DQL2 DFE Tap-2 - Q3’17 Ballot #1845.62................................................................ 91
3.5.87 MR147 (MA[7:0]=93H) - DQL2 DFE Tap-3 - Q3’17 Ballot #1845.62................................................................ 92
3.5.88 MR148 (MA[7:0]=94H) - DQL2 DFE Tap-4 - Q3’17 Ballot #1845.62................................................................ 93
3.5.89 MR149 through MR151 are undefined. ............................................................................................................ 93
3.5.90 MR152 (MA[7:0]=98H) - DQL3 DFE VGA - Q3’17 Ballot #1845.62 ................................................................. 94
3.5.91 MR153 (MA[7:0]=99H) - DQL3 DFE Tap-1 - Q3’17 Ballot #1845.62................................................................ 95
3.5.92 MR154 (MA[7:0]=9AH) - DQL3 DFE Tap-2 - Q3’17 Ballot #1845.62 ............................................................... 96
3.5.93 MR155 (MA[7:0]=9BH) - DQL3 DFE Tap-3 - Q3’17 Ballot #1845.62 ............................................................... 97
3.5.94 MR156 (MA[7:0]=9CH) - DQL3 DFE Tap-4 - Q3’17 Ballot #1845.62 ............................................................... 98
3.5.95 MR157 through MR159 are undefined. ............................................................................................................ 98
3.5.96 MR160 (MA[7:0]=A0H) - DQL4 DFE VGA - Q3’17 Ballot #1845.62 ................................................................. 99
3.5.97 MR161 (MA[7:0]=A1H) - DQL4 DFE Tap-1 - Q3’17 Ballot #1845.62 ............................................................... 100
3.5.98 MR162 (MA[7:0]=A2H) - DQL4 DFE Tap-2 - Q3’17 Ballot #1845.62 ............................................................... 101
3.5.99 MR163 (MA[7:0]=A3H) - DQL4 DFE Tap-3 - Q3’17 Ballot #1845.62 ............................................................... 102
3.5.100 MR164 (MA[7:0]=A4H) - DQL4 DFE Tap-4 - Q3’17 Ballot #1845.62 ............................................................. 103
3.5.101 MR165 through MR167 are undefined. .......................................................................................................... 103
3.5.102 MR168 (MA[7:0]=A8H) - DQL5 DFE VGA - Q3’17 Ballot #1845.62 ............................................................... 104
3.5.103 MR169 (MA[7:0]=A9H) - DQL5 DFE Tap-1- Q3’17 Ballot #1845.62 .............................................................. 105
3.5.104 MR170 (MA[7:0]=AAH) - DQL5 DFE Tap-2 - Q3’17 Ballot #1845.62............................................................. 106
3.5.105 MR171 (MA[7:0]=ABH) - DQL5 DFE Tap-3 - Q3’17 Ballot #1845.62............................................................. 107
3.5.106 MR172 (MA[7:0]=ACH) - DQL5 DFE Tap-4 - Q3’17 Ballot #1845.62............................................................. 108
3.5.107 MR173 through MR175 are undefined. .......................................................................................................... 108
3.5.108 MR176 (MA[7:0]=B0H) - DQL6 DFE VGA - Q3’17 Ballot #1845.62 ............................................................... 109
3.5.109 MR177 (MA[7:0]=B1H) - DQL6 DFE Tap-1- Q3’17 Ballot #1845.62 .............................................................. 110
3.5.110 MR178 (MA[7:0]=B2H) - DQL6 DFE Tap-2 - Q3’17 Ballot #1845.62 ............................................................. 111
3.5.111 MR179 (MA[7:0]=B3H) - DQL6 DFE Tap-3 - Q3’17 Ballot #1845.62 ............................................................. 112
3.5.112 MR180 (MA[7:0]=B4H) - DQL6 DFE Tap-4 - Q3’17 Ballot #1845.62 ............................................................. 113
3.5.113 MR181 through MR183 are undefined. .......................................................................................................... 113
3.5.114 MR184 (MA[7:0]=B8H) - DQL7 DFE VGA - Q3’17 Ballot #1845.62 ............................................................... 114
3.5.115 MR185 (MA[7:0]=B9H) - DQL7 DFE Tap-1 - Q3’17 Ballot #18
45.62 ............................................................. 115
3.5.116 MR186 (MA[7:0]=BAH) - DQL7 DFE Tap-2 - Q3’17 Ballot #1845.62............................................................. 116
