JEDEC Standard No. 209-5C
-i-
Low Power Double Data Rate (LPDDR) 5/5X
Contents
Page
1 Scope ......................................................................................................................................... 1
2 Overview .................................................................................................................................. 1
2.1 Features ..................................................................................................................................... 1
2.2 Functional Description .............................................................................................................. 1
2.2.1 Pad Definition and Description ................................................................................................. 3
2.2.2 Pin per Byte ............................................................................................................................... 4
2.2.3 LPDDR5/LPDDR5X Bank Architecture ................................................................................... 4
2.2.3.1 Block Diagram of Bank Configuration and Read Operation Outline ....................................... 5
2.2.3.1.1 4Banks / 4Bank Groups Configuration ..................................................................................... 5
2.2.3.1.2 8Banks Mode Configuration (Does not Apply to LPDDR5X SDRAM) .................................. 6
2.2.3.1.3 16Banks Mode Configuration ................................................................................................... 7
2.2.3.2 LPDDR5/LPDDR5X Address Translation Table ...................................................................... 8
2.2.3.3 Bank Architecture Transition ..................................................................................................... 8
2.2.3.4 Burst Operation ......................................................................................................................... 8
2.2.4 LPDDR5 SDRAM Addressing ................................................................................................ 14
2.3 Speed Grade ............................................................................................................................ 20
2.3.1 Burst Sequence ........................................................................................................................ 22
3 WCK Clocking ....................................................................................................................... 23
4 Initialization and Training .................................................................................................... 26
4.1 Power-up, Initialization, and Power-off Procedure ................................................................. 26
4.1.1 Voltage Ramp and Device Initialization .................................................................................. 26
4.1.2 Dual VDD2 Rail setting (MR13 OP[7]) and its Change ......................................................... 30
4.1.3 Reset Initialization with Stable Power .................................................................................... 30
4.1.4 Power-off Sequence ................................................................................................................. 31
4.1.5 Uncontrolled Power-off Sequence ........................................................................................... 31
4.2 Training ................................................................................................................................... 32
4.2.1 ZQ Calibration ......................................................................................................................... 32
4.2.1.1 Calibration During Powerup and Initialization ....................................................................... 32
4.2.1.1.1 Background Calibration .......................................................................................................... 33
4.2.1.1.2 Latching ZQ Calibration Results in Background Calibration Mode ....................................... 34
4.2.1.1.3 Command-Based Calibration .................................................................................................. 34
4.2.1.1.4 Latching ZQ Calibration Results in Command-Based Calibration Mode ............................... 35
4.2.1.1.5 Maintaining Accurate Calibration - Background Calibration Mode ....................................... 35
4.2.1.1.6 Maintaining Accurate Calibration – Command-Based Calibration Mode .............................. 36
4.2.1.1.7 Changing between Calibration Modes .................................................................................... 36
4.2.1.1.7.1 Changing between Calibration Modes when DVFSQ is not Active ....................................... 36
4.2.1.1.7.2 Changing between Calibration Modes when DVFSQ is Active .............................................. 37
4.2.1.2 ZQ Stop Functionality ............................................................................................................. 38
4.2.1.2.1 ZQ Resistor Sharing by other Device(s) ................................................................................. 38
4.2.1.2.1.1 ZQ Resistor Sharing in Background Calibration Mode .......................................................... 38
4.2.1.2.1.2 ZQ Resistor Sharing in Command-Based Calibration Mode .................................................. 38
Downloaded by Cherry Zhang (Cherry.Zhang@fci.com) on Jun 30, 2024, 9:01 pm PDT
Amphenol Corp
bzxylyz2024-08-27谢谢分享，正在找lpddr5x的资料，终于找到了。
