JESD79-5B DDR5 SDRAM-2022 JEDEC.pdf 最新版免费下载

1 Scope ............................................................................................................................................... 1

1.1 JM7 Verbal Forms and Terms ....................................................................................................... 1

2 DDR5 SDRAM Package, Pinout Description, and Addressing ......................................................... 2

2.1 DDR5 SDRAM Row for X4, X8 ...................................................................................................... 2

2.2 DDR5 SDRAM Ball Pitch ............................................................................................................... 2

2.3 DDR5 SDRAM Columns for X4, X8 ............................................................................................... 2

2.4 DDR5 SDRAM X4/8 Ballout Using MO-210 .................................................................................. 3

2.5 DDR5 SDRAM X16 Ballout Using MO-210 ................................................................................... 4

2.6 Pinout Description ......................................................................................................................... 5

3.3.2 Reset Initialization with Stable Power ......................................................................................... 14

3.3.3 Input Voltage Power-up and Power-Down Sequence ................................................................ 15

3.4 Mode Register Definition ............................................................................................................... 16

3.4.1 Mode Register Read (MRR) ....................................................................................................... 16

3.4.2 Mode Register WRITE (MRW) ................................................................................................... 20

3.4.3 DFE Mode Register Write Update Timing .................................................................................. 20

3.4.4 Mode Register Truth Tables and Timing Constraints .................................................................. 21

3.5 Mode Registers ............................................................................................................................. 24

3.5.1 Mode Register Assignment and Definition in DDR5 SDRAM .................................................... 24

3.5.2 MR0 (MA[7:0]=00H) Burst Length and CAS Latency ................................................................. 31

3.5.9 MR7 (MA[7:0]=07H) - Write Leveling Internal +0.5tCK Alignment Offset ................................... 39

3.5.10 MR8 (MA[7:0]=08H) - Preamble / Postamble ........................................................................... 40

3.5.11 MR9 (MA[7:0]=09H) - Writeback Suppression and TM ............................................................ 41

3.5.12 MR10 (MA[7:0]=0AH) - VrefDQ Calibration Value .................................................................... 42

3.5.13 MR11 (MA[6:0]=0BH) - Vref CA Calibration Value .................................................................... 43

3.5.14 MR12 (MA[7:0]=0CH) - Vref CS Calibration Value ................................................................... 44

3.5.15 MR13 (MA [7:0] = 0DH) - CS Geardown / tCCD_L / tCCD_L_WR / tCCD_L_WR2 / tDLLK .... 45

3.5.16 MR14 (MA[7:0]=0EH) - Transparency ECC Configuration ....................................................... 46

3.5.22 MR20 (MA [7:0] = 14H) - Error Count (EC) ............................................................................... 49

3.5.23 MR21 (MA [7:0] = 15H) - Rx CTLE Control Setting (DQS) ....................................................... 50

3.5.24 MR22 (MA [7:0] = 16H) - MBIST/mPPR Transparency, Rx CTLE Control Setting (Support

3.5.25 MR23 (MA [7:0] = 17H) - MBIST/PPR Settings ........................................................................ 52

3.5.26 MR24 (MA [7:0] = 18H) - PPR Guard Key ................................................................................ 53

3.5.27 MR25 (MA[7:0]=19H) - Read Training Mode Settings .............................................................. 53

3.5.28 MR26 (MA[7:0]=1AH) - Read Pattern Data0 / LFSR0 .............................................................. 54

3.5.29 MR27 (MA[7:0]=1BH) - Read Pattern Data1 / LFSR1 .............................................................. 54

3.5.30 MR28 (MA[7:0]=1CH) - Read Pattern Invert DQL7:0 (DQ7:0) ................................................. 55

3.5.37 MR35 (MA[7:0]=23H) - RTT_NOM_WR & RTT_NOM_RD ...................................................... 61

3.5.38 MR36 (MA[7:0]=24H) - RTT Loopback ..................................................................................... 62

3.5.39 MR37 (MA[7:0]= 25H) - ODTL Write Control Offset ................................................................. 63

3.5.40 MR38 (MA[7:0]=26H) - ODTL NT Write Control Offset ............................................................. 64

3.5.41 MR39 (MA[7:0]=27H) - ODTL NT Read Control Offset ............................................................ 65

3.5.42 MR40 (MA[7:0]=28H) - Read DQS Offset Timing ..................................................................... 66

3.5.43 MR41 (MA[7:0]=29H) - RFU - ................................................................................................... 66

3.5.44 MR42 (MA[7:0]=2AH) - DCA Types Supported ........................................................................ 67

3.5.45 MR43 (MA[7:0]=2BH) - DCA Settings 1 .................................................................................... 69

3.5.46 MR44 (MA[7:0]=2CH) - DCA Settings 2 ................................................................................... 70