JEDEC Standard No. 209-5B
ii
4.2.2.3 Command Bus Training Mode1 (FSP with DVFSQ enable) ......................................56
4.2.2.4 Command Bus Training Mode2 ................................................................................61
4.2.2.5 Command Bus Training Mode2 (FSP with DVFSQ enable) ......................................71
4.2.3 CA VREF Training ....................................................................................................76
4.2.4 DQ VREF Training ...................................................................................................76
4.2.5 WCK2CK Leveling ...................................................................................................76
4.2.5.1 WCK2CK Leveling Mode (write-leveling called in LPDDR4) .....................................76
4.2.5.2 WCK2CK Leveling Procedure and Related AC parameters ......................................77
4.2.6 Duty Cycle Adjuster (DCA) .......................................................................................80
4.2.6.1 Duty Cycle Adjuster Range ......................................................................................81
4.2.6.2 Relationship between WCK waveform and DCA Code Change ................................82
4.2.6.3 The relationship between DCA Code Change and DQ output/RDQS timing .............83
4.2.7 Read DCA (Duty Cycle Adjuster) ..............................................................................84
4.2.7.1 Read Duty Cycle Adjuster Range .............................................................................84
4.2.7.2 The relationship between Read DCA Code Change and DQ output/RDQS timing ...84
4.2.8 Duty Cycle Monitor (DCM) .......................................................................................85
4.2.8.1 DCM Functional Description .....................................................................................85
4.2.8.2 DCM Sequence ........................................................................................................86
4.2.9 READ DQ Calibration ...............................................................................................88
4.2.9.1 READ DQ Calibration Training Procedure ................................................................88
4.2.9.2 READ DQ Calibration Example ................................................................................92
4.2.9.3 READ DQ Calibration after Power Down Exit ...........................................................93
4.2.9.4 DMI Behavior Control for RDC .................................................................................94
4.2.9.4.1.1 DMI Output Behavior Mode 1 ...................................................................................94
4.2.9.4.1.2 DMI Output Behavior Mode 2 ...................................................................................94
4.2.10 WCK-DQ Training ....................................................................................................95
4.2.10.1 Training procedure ...................................................................................................96
4.2.10.1.1 Relationship between MR setting and FIFO training behavior ..................................97
4.2.10.1.1.1 DMI Output Behavior Mode 1 .............................................................................99
4.2.10.1.1.2 DMI Output Behavior Mode 2 .............................................................................99
4.2.10.2 WCK-RDQS_t/Parity Training ................................................................................. 100
4.2.10.3 FIFO Pointer Reset and Synchronism .................................................................... 100
4.2.10.4 Command constraints for Write/Read FIFO command ........................................... 105
4.2.11 RDQS toggle mode ................................................................................................ 107
4.2.12 Enhanced RDQS training mode ............................................................................. 110
4.2.13 Read/Write-based WCK-RDQS_t Training ............................................................. 114
4.2.13.1 Relationship between MR setting and Read/Write-based WCK-RDQS_t Training
behavior ........................................................................................................... 115
4.2.14 Rx Offset Calibration Training ................................................................................. 117
4.2.14.1 Offset Calibration Training Description ................................................................... 117
4.2.14.2 Offset Calibration Training Sequence ..................................................................... 117
5 Simplified LPDDR5 State Diagram
................................
......................................... 118
6 Mode Register Definition ........................................................................................ 123
6.1 Mode Register Assignment and Definition in LPDDR5 SDRAM .............................. 123
6.2 Mode Register Assignment and Definition in LPDDR5X SDRAM ........................... 126
6.3 Mode Register Definition ........................................................................................ 130
6.3.1 Mode Register definition ......................................................................................... 130
7 Operating ............................................................................................................... 188
7.1 Truth Table ............................................................................................................. 188
7.1.1 Command Truth Table ............................................................................................ 188
7.2 WCK Operation ...................................................................................................... 191
7.2.1 WCK2CK Synchronization operation ...................................................................... 191
7.2.1.1 WCK2CK Synchronization ..................................................................................... 191
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