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COVER PAGE

Conformance Test Suite

for

D-PHY

v1.2

CTS Version 1.0

03 February 2017

MIPI Board Approved 24 April 2017

This is an informative document, not a MIPI Specification.

Various rights and obligations that apply solely to MIPI Specifications (as defined in the MIPI Membership

Agreement and MIPI Bylaws) including, but not limited to, patent license rights and obligations, do not apply to

this document.

This document is subject to further editorial and technical development.

To check for the latest version, always refer to the MIPI Alliance Specifications Page:

https://members.mipi.org/wg/All-Members/home/approved-specs

Conformance Test Suite for D-PHY v1.2 CTS Version 1.0

03-Feb-2017

NOTICE OF DISCLAIMER

The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled

by any of the authors or developers of this material or MIPI®. The material contained herein is provided on an “AS

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nor does MIPI require or request the disclosure of any IPR or claims of IPR as respects the contents of this

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Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:

MIPI Alliance, Inc.

c/o IEEE-ISTO

445 Hoes Lane

Piscataway, NJ 08854

Attn: Board Secretary

Conformance Test Suite for D-PHY v1.2 CTS Version 1.0

03-Feb-2017

TABLE OF CONTENTS

COVER PAGE .............................................................................................................................. 1

TABLE OF CONTENTS .............................................................................................................. 3

DEVELOPMENT HISTORY ...................................................................................................... 7

INTRODUCTION......................................................................................................................... 9

REFERENCES ............................................................................................................................. 11

SECTION 1: TX TIMERS AND SIGNALING ........................................................................ 12

GROUP 1: DATA LANE LP-TX SIGNALING REQUIREMENTS ....................................................................... 13

Test 1.1.1 – Data Lane LP-TX Thevenin Output High Level Voltage (V

) ...................................................... 14

Test 1.1.2 – Data Lane LP-TX Thevenin Output Low Level Voltage (V

) ....................................................... 17

Test 1.1.3 – Data Lane LP-TX 15%-85% Rise Time (T

RLP

) ................................................................................ 19

Test 1.1.4 – Data Lane LP-TX 15%-85% Fall Time (T

FLP

) ................................................................................. 22

Test 1.1.5 – Data Lane LP-TX Slew Rate vs. C

LOAD

(δV/δt

) ........................................................................... 23

Test 1.1.6 – Data Lane LP-TX Pulse Width of Exclusive-OR Clock (T

LP-PULSE-TX

) ............................................ 31

Test 1.1.7 – Data Lane LP-TX Period of Exclusive-OR Clock (T

LP-PER-TX

) ........................................................ 34

GROUP 2: CLOCK LANE LP-TX SIGNALING REQUIREMENTS ................................................................... 36

Test 1.2.1 – Clock Lane LP-TX Thevenin Output High Level Voltage (V

) .................................................... 37

Test 1.2.2 – Clock Lane LP-TX Thevenin Output Low Level Voltage (V

) ..................................................... 39

Test 1.2.3 – Clock Lane LP-TX 15%-85% Rise Time (T

RLP

).............................................................................. 40

Test 1.2.4 – Clock Lane LP-TX 15%-85% Fall Time (T

FLP

) ............................................................................... 41

Test 1.2.5 – Clock Lane LP-TX Slew Rate vs. C

LOAD

(δV/δt

) ......................................................................... 42

GROUP 3: DATA LANE HS-TX SIGNALING REQUIREMENTS ...................................................................... 43

Test 1.3.1 – Data Lane HS Entry: Data Lane T

LPX

Value .................................................................................... 44

Test 1.3.2 – Data Lane HS Entry: T

HS-PREPARE

Value........................................................................................... 46

Test 1.3.3 – Data Lane HS Entry: T

HS-PREPARE

+ T

HS-ZERO

Value ......................................................................... 47

Test 1.3.4 – Data Lane HS-TX Differential Voltages (V

OD(0)

, V

OD(1)

). ................................................................ 48

Test 1.3.5 – Data Lane HS-TX Differential Voltage Mismatch (ΔV

) ............................................................. 52

Test 1.3.6 – Data Lane HS-TX Single-Ended Output High Voltages (V

OHHS(DP)

, V

OHHS(DN)

) .............................. 53

Test 1.3.7 – Data Lane HS-TX Static Common-Mode Voltages (V

CMTX(1)

, V

CMTX(0)

) ........................................ 56

Test 1.3.8 – Data Lane HS-TX Static Common-Mode Voltage Mismatch (ΔV

CMTX(1,0)

) .................................... 59

Test 1.3.9 – Data Lane HS-TX Dynamic Common-Level Variations Between 50-450MHz (ΔV

CMTX(LF)

) ........ 60

Test 1.3.10 – Data Lane HS-TX Dynamic Common-Level Variations Above 450MHz (ΔV

CMTX(HF)

) ............... 63

Test 1.3.11 – Data Lane HS-TX 20%-80% Rise Time (t

) ................................................................................. 64

Test 1.3.12 – Data Lane HS-TX 80%-20% Fall Time (t

) ................................................................................... 69

Test 1.3.13 – Data Lane HS Exit: T

HS-TRAIL

Value .............................................................................................. 71

Test 1.3.14 – Data Lane HS Exit: 30%-85% Post-EoT Rise Time (T

REOT

) ......................................................... 73

Test 1.3.15 – Data Lane HS Exit: T

EOT

Value ..................................................................................................... 75

Test 1.3.16 – Data Lane HS Exit: T

HS-EXIT

Value ................................................................................................ 76

GROUP 4: CLOCK LANE HS-TX SIGNALING REQUIREMENTS ................................................................... 78

Test 1.4.1 – Clock Lane HS Entry: T

LPX

Value ................................................................................................... 79

Test 1.4.2 – Clock Lane HS Entry: T

CLK-PREPARE

Value ....................................................................................... 80

Test 1.4.3 – Clock Lane HS Entry: T

CLK-PREPARE

CLK-ZERO

Value ..................................................................... 81

Test 1.4.4 – Clock Lane HS-TX Differential Voltages (V

OD(0)

, V

OD(1)

) ............................................................... 82

Test 1.4.5 – Clock Lane HS-TX Differential Voltage Mismatch (ΔV

) ........................................................... 85

Test 1.4.6 – Clock Lane HS-TX Single-Ended Output High Voltages (V

OHHS(DP)

, V

OHHS(DN)

) ............................ 86

Test 1.4.7 – Clock Lane HS-TX Static Common-Mode Voltages (V

CMTX(1)

, V

CMTX(0)

) ...................................... 89

Test 1.4.8 – Clock Lane HS-TX Static Common-Mode Voltage Mismatch (ΔV

CMTX(1,0)

) .................................. 90

Test 1.4.9 – Clock Lane HS-TX Dynamic Common-Level Variations Between 50-450MHz (ΔV

CMTX(LF)

) ...... 91

Test 1.4.10 – Clock Lane HS-TX Dynamic Common-Level Variations Above 450MHz (ΔV

CMTX(HF)

) ............. 92

Test 1.4.11 – Clock Lane HS-TX 20%-80% Rise Time (t

) ............................................................................... 93

Conformance Test Suite for D-PHY v1.2 CTS Version 1.0

03-Feb-2017

Test 1.4.12 – Clock Lane HS-TX 80%-20% Fall Time (t

) ................................................................................. 95

Test 1.4.13 – Clock Lane HS Exit: T

CLK-TRAIL

Value ........................................................................................... 97

Test 1.4.14 – Clock Lane HS Exit: 30%-85% Post-EoT Rise Time (T

REOT

) ....................................................... 99

Test 1.4.15 – Clock Lane HS Exit: T

EOT

Value ................................................................................................. 100

Test 1.4.16 – Clock Lane HS Exit: T

HS-EXIT

Value ............................................................................................ 101

Test 1.4.17 – Clock Lane HS Clock Instantaneous UI (UI

INST

) ......................................................................... 103

Test 1.4.18 – Clock Lane HS Clock Delta UI (ΔUI) ......................................................................................... 105

GROUP 5: HS-TX CLOCK-TO-DATA LANE TIMING REQUIREMENTS ...................................................... 107

Test 1.5.1 – HS Entry: T

CLK-PRE

Value ............................................................................................................... 108

Test 1.5.2 – HS Exit: T

CLK-POST

Value ............................................................................................................... 110

Test 1.5.3 – HS Clock Rising Edge Alignment to First Payload Bit ................................................................. 112

Test 1.5.4 – Data-to-Clock Skew (T

SKEW[TX]

) .................................................................................................... 114

Test 1.5.5 – Initial HS Skew Calibration Burst (T

SKEWCAL-SYNC

, T

SKEWCAL)

....................................................... 117

Test 1.5.6 – Periodic HS Skew Calibration Burst (T

SKEWCAL-SYNC

, T

SKEWCAL)

................................................... 119

GROUP 6: LP-TX INIT, ULPS, AND BTA REQUIREMENTS ........................................................................... 120

Test 1.6.1 – INIT: LP-TX Initialization Period (T

INIT,MASTER

) ........................................................................... 121

Test 1.6.2 – ULPS Entry: Verification of Clock Lane LP-TX ULPS support ................................................... 123

Test 1.6.3 – ULPS Exit: Transmitted T

WAKEUP

Interval ..................................................................................... 124

Test 1.6.4 – BTA: TX-Side T

TA-GO

Interval Value ............................................................................................ 126

Test 1.6.5 – BTA: RX-Side T

TA-SURE

Interval Value ......................................................................................... 128

Test 1.6.6 – BTA: RX-Side T

TA-GET

Interval Value ........................................................................................... 130

SECTION 2: RX TIMERS AND ELECTRICAL TOLERANCES ...................................... 132

GROUP 1: LP-RX VOLTAGE AND TIMING REQUIREMENTS ...................................................................... 133

Test 2.1.1 – LP-RX Logic 1 Input Voltage (V

) .............................................................................................. 134

Test 2.1.2 – LP-RX Logic 0 Input Voltage, Non-ULP State (V

) .................................................................... 136

Test 2.1.3 – LP-RX Logic 0 Input Voltage, ULP State (V

IL-ULPS

) (OBSOLETE) ............................................. 138

Test 2.1.4 – LP-RX Input Hysteresis (V

HYST

) .................................................................................................... 140

Test 2.1.5 – LP-RX Minimum Pulse Width Response (T

MIN-RX

) ....................................................................... 143

Test 2.1.6 – LP-RX Input Pulse Rejection (e

SPIKE

) ............................................................................................ 145

Test 2.1.7 – LP-RX Interference Tolerance (V

INT

and f

INT

) ............................................................................... 149

Test 2.1.8 – LP-CD Logic Contention Thresholds (V

IHCD

and V

ILCD

) (OBSOLETE) ....................................... 151

GROUP 2: LP-RX BEHAVIORAL REQUIREMENTS ....................................................................................... 153

Test 2.2.1 – LP-RX Initialization period (T

INIT

) ................................................................................................ 154

Test 2.2.2 – ULPS Exit: LP-RX T

WAKEUP

Timer Value ..................................................................................... 156

Test 2.2.3 – Clock Lane LP-RX Invalid/Aborted ULPS Entry .......................................................................... 157

Test 2.2.4 – Data Lane LP-RX Invalid/Aborted Escape Mode Entry ................................................................ 159

Test 2.2.5 – Data Lane LP-RX Invalid/Aborted Escape Mode Command ........................................................ 161

Test 2.2.6 – Data Lane LP-RX Escape Mode Invalid Exit (OBSOLETE) ........................................................ 163

Test 2.2.7 – Data Lane LP-RX Escape Mode, Ignoring of Post-Trigger-Command Extra Bits ........................ 165

Test 2.2.8 – Data Lane LP-RX Escape Mode Unsupported/Unassigned Commands ........................................ 167

GROUP 3: HS-RX VOLTAGE AND SETUP/HOLD REQUIREMENTS ........................................................... 169

Test 2.3.1 – HS-RX Common Mode Voltage Tolerance (V

CMRX(DC)

)................................................................ 170

Test 2.3.2 – HS-RX Differential Input High Threshold (V

IDTH

) ........................................................................ 172

Test 2.3.3 – HS-RX Differential Input Low Threshold (V

IDTL

) ......................................................................... 174

Test 2.3.4 – HS-RX Single-Ended Input High Voltage (V

IHHS

) ........................................................................ 176

Test 2.3.5 – HS-RX Single-Ended Input Low Voltage (V

ILHS

) ......................................................................... 178

Test 2.3.6 – HS-RX Common-Mode Interference 50MHz - 450MHz (ΔV

CMRX(LF)

) ......................................... 180

Test 2.3.7 – HS-RX Common-Mode Interference Beyond 450MHz (ΔV

CMRX(HF)

) ........................................... 182

Test 2.3.8 – HS-RX Setup/Hold and Jitter Tolerance ........................................................................................ 183

GROUP 4: HS-RX TIMER REQUIREMENTS .................................................................................................... 189

Test 2.4.1 – Data Lane HS-RX T

D-TERM-EN

Value .............................................................................................. 190

Test 2.4.2 – Data Lane HS-RX T

HS-PREPARE

+ T

HS-ZERO

Tolerance ..................................................................... 192

Test 2.4.3 – Data Lane HS-RX T

HS-SETTLE

Value ............................................................................................... 194

Test 2.4.4 – Data Lane HS-RX T

HS-TRAIL

Tolerance .......................................................................................... 197

Test 2.4.5 – Data Lane HS-RX T

HS-SKIP

Value .................................................................................................. 199

Conformance Test Suite for D-PHY v1.2 CTS Version 1.0

03-Feb-2017

Test 2.4.6 – Clock Lane HS-RX T

CLK-TERM-EN

Value ......................................................................................... 201

Test 2.4.7 – Clock Lane HS-RX T

CLK-PREPARE

+ T

CLK-ZERO

Tolerance ............................................................... 203

Test 2.4.8 – Clock Lane HS-RX T

CLK-SETTLE

Value ........................................................................................... 205

Test 2.4.9 – Clock Lane HS-RX T

CLK-TRAIL

Tolerance ...................................................................................... 207

Test 2.4.10 – Clock Lane HS-RX T

CLK-MISS

Value (OBSOLETE) .................................................................... 209

Test 2.4.11 – Clock Lane HS-RX T

CLK-PRE

and T

CLK-POST

Tolerance ................................................................ 211

SECTION 3: INTERFACE IMPEDANCE AND S-PARAMETERS................................... 213

GROUP 1: HS-TX S-PARAMETERS .................................................................................................................. 214

Test 3.1.1 – HS-TX Differential Return Loss (SDD22) .................................................................................... 215

Test 3.1.2 – HS-TX Common-Mode Return Loss (SCC22) .............................................................................. 219

Test 3.1.3 – HS-TX Mode Conversion Limits (SDC22) ................................................................................... 221

Test 3.1.4 – HS-TX Single-Ended Output Impedance (Z

) ............................................................................. 223

Test 3.1.5 – HS-TX Single-Ended Output Impedance Mismatch (ΔZ

) .......................................................... 225

GROUP 2: HS-RX S-PARAMETERS .................................................................................................................. 226

Test 3.2.1 – HS-RX Differential Return Loss (SDD11) .................................................................................... 227

Test 3.2.2 – HS-RX Common-Mode Return Loss (SCC11) .............................................................................. 229

Test 3.2.3 – HS-RX Mode Conversion Limits (SDC11) ................................................................................... 232

Test 3.2.4 – HS-RX DC Differential Input Impedance (Z

) ............................................................................. 234

GROUP 3: LP-TX/RX IMPEDANCE REQUIREMENTS ................................................................................... 236

Test 3.3.1 – LP-TX Output Impedance (Z

OLP

) ................................................................................................... 237

Test 3.3.2 – LP-RX Input Leakage Current (I

LEAK

) ........................................................................................... 239

ANNEXES ................................................................................................................................. 241

ANNEX A: RESOURCE REQUIREMENTS (DUT AND TEST EQUIPMENT) .................................................................. 242

A.1: LP/HS Transmitter Tests ........................................................................................................................... 242

A.2: Receiver Tests ............................................................................................................................................ 244

ANNEX B: TEST SETUPS ........................................................................................................................................ 245

B.1: Transmitter Tests ....................................................................................................................................... 245

B.1.1: LP Transmitter Tests ........................................................................................................................... 245

B.1.2: HS Transmitter Tests .......................................................................................................................... 246

B.1.3: Bus Turnaround Tests ......................................................................................................................... 247

B.2: Receiver Tests ............................................................................................................................................ 248

B.3: Interface Impedance and S-Transmitter Tests ............................................................................................ 250

B.3.1: Impedance and S-Parameter Tests ...................................................................................................... 250

B.3.2: LP-TX Output Impedance ................................................................................................................... 250

B.3.3: LP-RX Input Leakage Current ............................................................................................................ 251

ANNEX C: GENERIC RECEIVER TEST SEQUENCE TEMPLATE .................................................................................. 252

C.1: Introduction ................................................................................................................................................ 252

C.2: General Test Sequence Framework ........................................................................................................... 252

ANNEX D: REFERENCE HS TEST PATTERN FOR RX BER VERIFICATION AND INTEROPERABILITY TESTING .......... 255

D.1: Introduction ............................................................................................................................................... 255

D.2: Background / Overview ............................................................................................................................. 255

D.3: Considerations for D-PHY......................................................................................................................... 256

D.4: Scalability .................................................................................................................................................. 256

D.5: Scalable CSI/DSI Composite Pattern......................................................................................................... 256

D.6: Notes on Pattern Structure and Subpattern Ordering ................................................................................. 258

D.7: Datatype-Specific Payload Formatting ...................................................................................................... 258

D.8: Framing of the Payload Pattern ................................................................................................................. 260

ANNEX E: LOGIC ANALYZER TRIGGER SETUP FOR FRAME ERROR COUNTING (INFORMATIVE) ............................. 261

E.1: Introduction ................................................................................................................................................ 261

E.2: Trigger Setup .............................................................................................................................................. 261

ANNEX F: STATISTICAL METHODOLOGY FOR BIT ERROR RATE (BER) VERIFICATION ........................................... 264

F.1: Introduction ................................................................................................................................................ 264

F.2: Statistical Model ......................................................................................................................................... 264

F.3: Hypothesis Test .......................................................................................................................................... 265

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