Conformance Test Suite for D-PHY v2.1 CTS Version 1.0
22-Oct-2018
iv Copyright © 2007-2018 MIPI Alliance, Inc.
All rights reserved.
Confidential
Test 1.3.8 Data Lane HS-TX Static Common-Mode Voltage Mismatch (ΔV
CMTX(1,0)
) ....... 68
Test 1.3.9 Data Lane HS-TX Dynamic Common-Level Variations Between
50 MHz – 450 MHz (ΔV
CMTX(LF)
) ....................................................................... 70
Test 1.3.10 Data Lane HS-TX Dynamic Common-Level Variations Above
450 MHz (ΔV
CMTX(HF)
) ........................................................................................ 74
Test 1.3.11 Data Lane HS-TX 20%-80% Rise Time (t
R
) ...................................................... 76
Test 1.3.12 Data Lane HS-TX 80%-20% Fall Time (t
F
) ....................................................... 82
Test 1.3.13 Data Lane HS Exit: T
HS-TRAIL
Value .................................................................... 85
Test 1.3.14 Data Lane HS Exit: 30%-85% Post-EoT Rise Time (T
REOT
) .............................. 87
Test 1.3.15 Data Lane HS Exit: T
EOT
Value ........................................................................... 89
Test 1.3.16 Data Lane HS Exit: T
HS-EXIT
Value ...................................................................... 91
Group 4 Clock Lane HS-TX Signaling Requirements ..................................................... 94
Test 1.4.1 Clock Lane HS Entry: T
LPX
Value ...................................................................... 95
Test 1.4.2 Clock Lane HS Entry: T
CLK-PREPARE
Value .......................................................... 97
Test 1.4.3 Clock Lane HS Entry: T
CLK-PREPARE
+T
CLK-ZERO
Value ......................................... 99
Test 1.4.4 Clock Lane HS-TX Differential Voltages (V
OD(0)
, V
OD(1)
) ................................ 101
Test 1.4.5 Clock Lane HS-TX Differential Voltage Mismatch (ΔV
OD
) ............................. 105
Test 1.4.6 Clock Lane HS-TX Single-Ended Output High Voltages
(V
OHHS(DP)
, V
OHHS(DN)
) ........................................................................................ 107
Test 1.4.7 Clock Lane HS-TX Static Common-Mode Voltages (V
CMTX(1)
, V
CMTX(0)
) ........ 111
Test 1.4.8 Clock Lane HS-TX Static Common-Mode Voltage Mismatch (ΔV
CMTX(1,0)
) ... 113
Test 1.4.9 Clock Lane HS-TX Dynamic Common-Level Variations Between
50 MHz – 450 MHz (ΔV
CMTX(LF)
) ..................................................................... 114
Test 1.4.10 Clock Lane HS-TX Dynamic Common-Level Variations Above
450 MHz (ΔV
CMTX(HF)
) ...................................................................................... 116
Test 1.4.11 Clock Lane HS-TX 20%-80% Rise Time (t
R
) .................................................. 118
Test 1.4.12 Clock Lane HS-TX 80%-20% Fall Time (t
F
) ................................................... 121
Test 1.4.13 Clock Lane HS Exit: T
CLK-TRAIL
Value .............................................................. 124
Test 1.4.14 Clock Lane HS Exit: 30%-85% Post-EoT Rise Time (T
REOT
) .......................... 126
Test 1.4.15 Clock Lane HS Exit: T
EOT
Value ....................................................................... 127
Test 1.4.16 Clock Lane HS Exit: T
HS-EXIT
Value .................................................................. 129
Test 1.4.17 Clock Lane HS Clock Instantaneous UI (UI
INST
) ............................................. 131
Test 1.4.18 Clock Lane HS Clock Delta UI (ΔUI) .............................................................. 134
Test 1.4.19 TX Spread Spectrum Clocking (SSC) Requirements ....................................... 136
Test 1.4.20 Clock Lane HS Clock Period Jitter ................................................................... 140
Group 5 HS-TX Clock-To-Data Lane Timing Requirements ........................................ 142
Test 1.5.1 HS Entry: T
CLK-PRE
Value .................................................................................. 143
Test 1.5.2 HS Exit: T
CLK-POST
Value ................................................................................... 145
Test 1.5.3 HS Clock Rising Edge Alignment to First Payload Bit .................................... 147
Test 1.5.4 Data-to-Clock Skew (T
SKEW[TX]
) ....................................................................... 150
Test 1.5.5 Initial HS Skew Calibration Burst (T
SKEWCAL-SYNC
, T
SKEWCAL)
.......................... 154
Test 1.5.6 Periodic HS Skew Calibration Burst (T
SKEWCAL-SYNC
, T
SKEWCAL)
...................... 157
Test 1.5.7 HS-TX Data and Clock Eye Diagram............................................................... 158
Test 1.5.8 Alternate Calibration Sequence (T
ALTCAL-SYNC
, T
ALTCAL
) ................................... 163
Test 1.5.9 Preamble Sequence (T
PREAMBLE
, T
EXTSYNC
) ....................................................... 166
Test 1.5.10 Clock and Data Lane TX HS-Idle: T
HS-IDLE-POST
, T
HS-IDLE-CLKHS0,
T
HS-IDLE-PRE
Values ............................................................................................. 169
