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Confidential

Conformance Test Suite

for

C-PHY

Specification

v2.1

CTS Version 1.0

25 August 2021

MIPI Board Approved 23 October 2021

This is an informative document, not a MIPI Specification.

Various rights and obligations that apply solely to MIPI Specifications (as defined in the MIPI

Membership Agreement and MIPI Bylaws) including, but not limited to, patent license rights and

obligations, do not apply to this document.

Further technical changes to this document are expected as work continues in the

C-PHY Working Group.

To check for the latest version, always refer to the MIPI Alliance Specifications Page:

https://members.mipi.org/wg/All-Members/home/approved-specs

Conformance Test Suite for C-PHY v2.1 CTS Version 1.0

25-Aug-2021

Confidential

NOTICE OF DISCLAIMER

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Attn: Managing Director

CTS Version 1.0  Conformance Test Suite for C-PHY v2.1 
25-Aug-2021 
  Copyright © 2007–2021 MIPI Alliance, Inc.  iii 
  All rights reserved. 
  Confidential 
Contents 
 
Figures   .................................................................................................................................. vii 
Tables   ................................................................................................................................. xiii 
Release History ............................................................................................................................ xiv 
Introduction .................................................................................................................................. 15 
Terminology .................................................................................................................................. 17 
Use of Special Terms .............................................................................................................................. 17 
Abbreviations ......................................................................................................................................... 17 
Acronyms ................................................................................................................................................ 18 
References   ................................................................................................................................... 19 
Section 1  TX Timers and Signaling ........................................................................................ 21 
Overview ................................................................................................................................................. 21 
Group 1  LP-TX Signaling Requirements ............................................................................................ 22 
Test 1.1.1  Thevenin Output High Level Voltage (V
OH
) ..................................................................... 23 
Test 1.1.2  LP-TX Thevenin Output Low Level Voltage (V
OL
) .......................................................... 26 
Test 1.1.3  LP-TX 15%-85% Rise Time (t
RLP
) ................................................................................... 28 
Test 1.1.4  LP-TX 15%-85% Fall Time (t
FLP
) ..................................................................................... 31 
Test 1.1.5  LP-TX Slew Rate vs. C
LOAD
 (δV/δt
SR
) .............................................................................. 32 
Test 1.1.6  LP-TX Pulse Width of Exclusive-OR Clock (t
LP-PULSE-TX
) ................................................ 38 
Test 1.1.7  LP-TX Period of Exclusive-OR Clock (t
LP-PER-TX
) ............................................................ 41 
Test 1.1.8  t
LP-EXIT
 Value ..................................................................................................................... 43 
Group 2  HS-TX Signaling Requirements ............................................................................................ 46 
Test 1.2.1  t
LPX
 Duration ..................................................................................................................... 48 
Test 1.2.2  t
3-PREPARE
 Duration ............................................................................................................. 50 
Test 1.2.3  t
3-PREBEGIN
 Duration ........................................................................................................... 52 
Test 1.2.4  t
3-PROGSEQ
 Duration ............................................................................................................ 54 
Test 1.2.5  t
3-PREEND
 Duration .............................................................................................................. 56 
Test 1.2.6  t
3-SYNC
 Duration ................................................................................................................. 58 
Test 1.2.7  HS-TX Differential Voltages (V
OD_AB
, V
OD_BC
, V
OD_CA
) ................................................... 61 
Test 1.2.8  HS-TX Differential Voltage Mismatch (ΔV
OD
) ................................................................ 66 
Test 1.2.9  HS-TX Single-Ended Output High Voltages (V
OHHS(VA)
, V
OHHS(VB), 
V
OHHS(VC)
) ................ 68 
Test 1.2.10  HS-TX Static Common-Point Voltages (V
CPTX
) ............................................................... 71 
Test 1.2.11  HS-TX Static Common-Point Voltage Mismatch (ΔV
CPTX(HS)
) ......................................... 75 
Test 1.2.12  HS-TX Dynamic Common-Point Variations Between 50-450 MHz (ΔV
CPTX(LF)
) ............ 77 
Test 1.2.13  HS-TX Dynamic Common-Point Variations Above 450 MHz (ΔV
CPTX(HF)
) .................... 80 
Test 1.2.14  HS-TX Rise Time (t
R
) (OBSOLETE) ............................................................................... 82 
Test 1.2.15  HS-TX Fall Time (t
F
) (OBSOLETE) ................................................................................ 84 
Test 1.2.16  t
3-POST
 Duration .................................................................................................................. 86 
Test 1.2.17  30%-85% Post-EoT Rise Time (t
REOT
) .............................................................................. 89 
Test 1.2.18  t
HS-EXIT
 Value ..................................................................................................................... 91 
Test 1.2.19  HS Clock Instantaneous UI (UI
INST
) ................................................................................. 93 
Test 1.2.20  HS Clock Delta UI (ΔUI) (OBSOLETE) .......................................................................... 95 
Test 1.2.21  HS-TX Eye Diagram......................................................................................................... 97 
Test 1.2.22  HS-TX UI Jitter (UI_Jitter
PEAK_TX
) ................................................................................. 109 

Conformance Test Suite for C-PHY v2.1  CTS Version 1.0 
  25-Aug-2021 
iv  Copyright © 2007–2021 MIPI Alliance, Inc. 
  All rights reserved. 
  Confidential 
Group 3  LP-TX INIT, ULPS, and BTA Requirements .................................................................... 114 
Test 1.3.1  INIT: LP-TX Initialization Period (t
INIT,PRIMARY
) ............................................................. 115 
Test 1.3.2  ULPS Exit: Transmitted t
WAKEUP
 Interval ........................................................................ 117 
Test 1.3.3  BTA: TX-Side t
TA-GO
 Interval Value ................................................................................ 119 
Test 1.3.4  BTA: RX-Side t
TA-SURE
 Interval Value ............................................................................. 121 
Test 1.3.5  BTA: RX-Side t
TA-GET
 Interval Value .............................................................................. 123 
Group 4  HS-TX Burst Signaling Requirements HS Unterminated Mode ..................................... 125 
Test 1.4.1  HS-TX Differential Voltages Unterminated (V
OD(UT)-AB
, V
OD(UT)-BC
, V
OD(UT)-CA
) ............ 126 
Test 1.4.2  HS-TX Differential Voltage Mismatch Unterminated (ΔV
OD(UT)
)................................... 130 
Test 1.4.3  HS-TX Single-Ended Output High Voltages Unterminated 
(V
OHHS(UT)(VA)
, V
OHHS(UT)(VB), 
V
OHHS(UT)(VC)
)...................................................................... 132 
Test 1.4.4  HS-TX Static Common-Point Voltages Unterminated (V
CPTX(UT)
) ................................. 135 
Group 5  HS-TX Calibration Preamble Signaling Requirements .................................................... 138 
Test 1.5.1  t
3-CALPREAMBLE
 Duration (Informative) ............................................................................. 139 
Test 1.5.2  t
3-ASID
 Duration (Informative).......................................................................................... 141 
Test 1.5.3  t
3-CALALTSEQ
 Duration (Informative) ................................................................................. 143 
Test 1.5.4  Calibration Sequence t
3-SYNC
 Duration (Informative) ...................................................... 145 
Section 2  RX Timers and Electrical Tolerances .................................................................. 149 
Overview ............................................................................................................................................... 149 
Group 1  LP-RX Voltage and Timing Requirements ........................................................................ 150 
Test 2.1.1  LP-RX Logic 1 Input Voltage (V
IH
) ................................................................................ 151 
Test 2.1.2  LP-RX Logic 0 Input Voltage, Non-ULP State (V
IL
) ...................................................... 153 
Test 2.1.3  LP-RX Input Hysteresis (V
HYST
) ..................................................................................... 155 
Test 2.1.4  LP-RX Minimum Pulse Width Response (t
MIN-RX
) ......................................................... 158 
Test 2.1.5  LP-RX Input Pulse Rejection (e
SPIKE
) (OBSOLETE) ..................................................... 160 
Group 2  LP-RX Behavioral Requirements ....................................................................................... 164 
Test 2.2.1  LP-RX Initialization period (t
INIT
) .................................................................................. 165 
Test 2.2.2  ULPS Exit: LP-RX t
WAKEUP
 Timer Value ........................................................................ 167 
Test 2.2.3  LP-RX Invalid/Aborted Escape Mode Entry .................................................................. 168 
Test 2.2.4  LP-RX Invalid/Aborted Escape Mode Command .......................................................... 170 
Test 2.2.5  LP-RX Escape Mode, Ignoring of Post-Trigger-Command Extra Bits ........................... 173 
Test 2.2.6  LP-RX Escape Mode Unsupported/Unassigned Commands .......................................... 175 
Group 3  HS-RX Voltage and Jitter Tolerance Requirements .......................................................... 177 
Test 2.3.1  HS-RX Amplitude Tolerance (V
CPRX(DC)
, V
IHHS
, V
ILHS
) .................................................. 178 
Test 2.3.2  HS-RX Differential Input High/Low Thresholds (V
IDTH
, V
IDTL
) (Informative) .............. 183 
Test 2.3.3  HS-RX Jitter Tolerance ................................................................................................... 185 
Test 2.3.4  HS-RX UI Jitter Tolerance (UI_Jitter
PEAK_RX
) ................................................................ 196 
Group 4  HS-RX Timer Requirements ............................................................................................... 200 
Test 2.4.1  HS-RX t
3-TERM-EN
 Duration.............................................................................................. 201 
Test 2.4.2  HS-RX t
3-PREPARE
 Tolerance ............................................................................................ 203 
Test 2.4.3  HS-RX t
3-PREBEGIN
 Tolerance ........................................................................................... 205 
Test 2.4.4  HS-RX t
3-PROGSEQ
 Tolerance ............................................................................................ 207 
Test 2.4.5  Test 2.4.5 HS-RX t
3-POST
 Tolerance ................................................................................. 209 

CTS Version 1.0  Conformance Test Suite for C-PHY v2.1 
25-Aug-2021 
  Copyright © 2007–2021 MIPI Alliance, Inc.  v 
  All rights reserved. 
  Confidential 
Section 3  Interface Impedance and S-Parameters .............................................................. 213 
Overview ............................................................................................................................................... 213 
Group 1  HS-TX S-Parameters and Impedance ................................................................................ 214 
Test 3.1.1  HS-TX Differential Return Loss (Sdd
TX
) ........................................................................ 215 
Test 3.1.2  HS-TX Common-Mode Return Loss (Scc
TX
) ................................................................. 218 
Test 3.1.3  HS-TX Mode Conversion Limits (SDC22) (OBSOLETE) ............................................ 220 
Test 3.1.4  HS-TX Single-Ended Output Impedance (Z
OS
) .............................................................. 222 
Test 3.1.5  HS-TX Single-Ended Output Impedance Mismatch (ΔZ
OS
) ........................................... 224 
Group 2  HS-RX S-Parameters and Impedance ................................................................................ 226 
Test 3.2.1  HS-RX Differential Return Loss (Sdd
RX
) ....................................................................... 227 
Test 3.2.2  HS-RX Common-Mode Return Loss (Scc
RX
) ................................................................. 230 
Test 3.2.3  HS-RX Mode Conversion Limits (SDC11) .................................................................... 233 
Test 3.2.4  HS-RX Differential Input Impedance (Z
ID
) .................................................................... 235 
Test 3.2.5  HS-RX Differential Input Impedance Mismatch (ΔZ
ID
) ................................................. 238 
Group 3  LP-TX/RX Impedance Requirements ................................................................................ 240 
Test 3.3.1  LP-TX Output Impedance (Z
OLP
) .................................................................................... 241 
Test 3.3.2  LP-RX Input Leakage Current (I
LEAK
) ............................................................................ 244 
Group 4  HS-TX Impedance Unterminated Mode ............................................................................ 247 
Test 3.4.1  HS-TX Single-Ended Output Impedance Unterminated (Z
OS(UT)
) .................................. 248 
Test 3.4.2  HS-TX Single-Ended Output Impedance Mismatch Unterminated (ΔZ
OS(UT)
) ............... 250 
Group 5  HS-RX Impedance Unterminated Mode ............................................................................ 252 
Test 3.5.1  HS-RX Differential Input Impedance Unterminated (Z
ID(UT)
) ........................................ 253 
Annexes   ................................................................................................................................. 255 
Overview ............................................................................................................................................... 255 
Scope of Tests ........................................................................................................................................ 255 
Annex A  Resource Requirements (DUTs and Test Equipment) ........................................ 257 
A.1  LP/HS Transmitter Tests ..................................................................................................... 258 
A.2  Receiver Tests ....................................................................................................................... 260 
A.3  S-Parameter and Impedance Tests ..................................................................................... 261 
Annex B  Test Setups .............................................................................................................. 263 
B.1  Transmitter Tests .................................................................................................................. 264 
B.1.1  LP Transmitter Tests ............................................................................................................... 264 
B.1.2  HS Transmitter Tests .............................................................................................................. 265 
B.1.3  Bus Turnaround Tests ............................................................................................................. 270 
B.2  Receiver Tests ....................................................................................................................... 271 
B.3  Other Tests ............................................................................................................................ 273 
B.3.1  Impedance and S-Parameter Tests .......................................................................................... 273 
B.3.2  LP-TX Output Impedance ...................................................................................................... 273 
B.3.3  LP-RX Input Leakage Current ............................................................................................... 274 
B.3.4  HS-RX Differential Input Impedance Unterminated ............................................................. 274 
Annex C  Statistical Methodology for Bit Error Rate (BER) Verification ........................ 275 
C.1  Introduction .......................................................................................................................... 276 
C.2  Statistical Model ................................................................................................................... 276 
C.3  Hypothesis Test ..................................................................................................................... 277 
C.4  Confidence Interval.............................................................................................................. 278 
C.5  Sample Test Construction .................................................................................................... 280 
C.6  Packet Error Rate Measurement ........................................................................................ 281 