MIPI_D-PHY_Specification_v01-00-00.pdf

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MIPI_D-PHY_Specification_v01-00-00.pdf MIPI Alliance Specification for D-PHY 想研究MIPI物理层的同学们赶快来学习,125页文档
Version1.00.0014-May-2009 MIPI Alliance Specification for D-PHY 2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or 3 controlled by any of the authors or developers of this material or MIPl. The material contained herein is 4 provided on an"as iS basis and to the maximum extent permitted by applicable law, this material is 5 provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIP 6 hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not 7 limited to, any (ifany)inplied warranties, duties or conditions of merchantability, of fitness for a 8 particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of 9 viruses, and of lack of negligence 10 All materials contained herein are protected by copyright laws, and may not be reproduced, republished distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express 12 prior written permission of MIPI Alliance. MIPl, MIPI Alliance and the dotted rainbow arch and all related 3 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and 14 cannot be used without its express prior written permission 15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET 16 POSSESSION. CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH 17 REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT.IN NO EVENT WILL I8 ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT 9 OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE 20 GOODS OR SERVICES. LOST PROFITS. LOSS OF USE. LOSS OF DATA OR ANY INCIDENTAL. 21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER 22 CONTRACT TORT WARRANTY OR OTHERWISE ARISING IN ANY WAY OUT OF THIS OR 23 ANY OTHER AGREEMENT SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL 24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH 25 DAMAGES 26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is 27 further notified that MIPI: (a)does not evaluate, test or verify the accuracy, soundness or credibility of the 28 contents of this Document;(b)does not monitor or enforce compliance with the contents of this Document 29 and (c)does not certify, test, or in any manner investigate products or services or any claims of compliance 30 with the contents of this Document. The use or implementation of the contents of this Document may 31 involve or require the use of intellectual property rights ("IPR")including(but not limited to) patents 32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPIMIPI 33 does not make any search or investigation for IPR, nor does miPi require or request the disclosure of any 34 IPR or claims of IPR as respects the contents of this document or otherwise 35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed 36 MIPI Alliance. Inc 37 c/o IEEE-ISTO 38 445 Hoes lane 39 Piscataway, NJ08854 40 Alin: Board Secretary Copyright C 2007-2009 MIPl Alliance, Inc. All rights reserved MIPI Alliance Member Confidential Version1.00.0014-May-2009 MIPI Alliance Specification for D-PHY 42 Contents 43 Draft Version 1.00.00-14 May 2009 441 Overview 14 5 1.2 Purpose.…..,.,.,,.,.. 472 Terminology… 2.1 Definitions 16 2.2 Abbreviations… 17 2.3 Acronyms 51 3 D-PHY Introduction 52 3.1 Summary of Phy functionality 53 3.2 Mandatory Functionality ················ 20 54 4 Architecture 21 55 4.1 Lane modules… 56 4.2 Master and slave 22 5 4.3 High Frequency Clock Generation 22 58 4.4 Clock lane data lanes and the phy-Protocol interface .22 4.5 Selectable Lane Options ·;···················· 23 4.6 Lane Module Types 4.6.1 Unidirectional Data Lane …26 4.6.2 Bi-directional data lanes 26 63 4.6.3 Clock lane .27 4.7 Configurations…. 7 65 4.7.1 Unidirectional Configurations............ 66 4.7.2Bi-D al Half-Duplex Configurations 67 4.7.3 Mixed Data Lane configurations 32 Copyright C 2007-2009 MIPl Alliance, Inc. All rights reserved MIPI Alliance Member Confidential 111 Ⅴ ersion1.00.0014-May-2009 MIPI Alliance Specification for D-PHY 69 5.1 Transmission Data Structure,……………………… ∴33 5.1.1 Data units a 勹 5.1.2 Bit order Serialization and De-Serialization 33 72 5.1.3 Encoding and decoding 73 5.1.4 Data Buffering ,33 74 5.2 Lane States and Line levels 75 5.3 Operating Modes: Control, High-Speed, and Escape 5. 4 High-Speed Data Transmission ··········;· 5. 41 Burst payload data 78 5.4.2 Start-of-Transmission 79 5.4.3 End-of-transmission 80 5.4.4 HS Data Transmission burst .36 5.5 Bi-directional data Lane turnaround 5.6 Escape Mode 41 83 5.6.1 Remote triggers 42 84 5.6.2 Low-Power data Transmission 43 85 5.6.3 Ultra-Low Power State 86 5.6.4 Escape Mode State Machine 43 87 5.7 High-Speed Clock Transmission 88 5. 8 Clock lane Ultra-Low Power State 50 9 59 Global Operation Timing Parameters.…… 5.10 System Power States 56 91 5.11 Initialization 56 92 5.12 Calibration 5.13 Global Operation Flow Diagram 57 94 5.14 Data Rate Dependent Parameters(informative) 95 5. 14.1 Parameters Containing Only UI values 96 5. 14.2 Parameters Containing Time and Ul values 59 Copyright C 2007-2009 MIPl Alliance, Inc. All rights reserved MIPI Alliance Member Confidential Version1.00.0014-May-2009 MIPI Alliance Specification for D-PHY 5.14.3 Parameters Containing Only Time Values………… 5.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent 6 Fault detection 61 100 6.1 Contention detection 101 6.2 Sequence Error Detection.…… 61 102 6.2.1 SoT Error 62 103 6.2.2 SOT Sync Error 104 6.2.3 EoT Sync Error 105 6.2. 4 Escape Mode Entry Command error. 106 6.2.5 LP Transmission Sync error 62 107 6.2.6 False Control error 108 6.3 Protocol Watchdog Timers(informative) 62 l09 6.3.1 HS RX Timeout 6.3.2 HS TX Timeout……………… ·················+···:··:················· ∴62 l11 6.3.3 Escape mode timeout 62 l12 6.3. 4 Escape Mode Silence Timeout 6.3.5 Turnaround errors 114 7 Interconnect and Lane Configuration .64 115 7.1 Lane configuration 116 7.2 Boundary Conditions..... …64 7.3 Definitions ………64 l18 7.4S- parameter Specifications………… .65 119 7.5 Characterization Conditions 20 7.6 nterconnect Specifications……… 121 7.6.1 Differential characteristics 122 7. 6.2 Common-mode characteristics 67 123 7.6.3 Intra-Lane Cross-Coupling 124 7. 6. 4 Mode-Conversion limits Copyright C 2007-2009 MIPl Alliance, Inc. All rights reserved MIPI Alliance Member Confidential Version1.00.0014-May-2009 MIPI Alliance Specification for D-PHY 125 7.6.5 Inter-Lane Cross-Coupling 67 126 7. 6.6 Inter-Lane static skew 127 7.7 Driver and receiver Characteristics 128 7.7.1 Differential Characteristics 129 7. 7.2 Common-Mode characteristics 130 7.7.3 Mode-Conversion Limits 131 7.7.4 Inter-Lane Matching 132 8 Electrical Characterislics 70 133 8.1 Driver characteristics 134 8.1.1 High-Speed Transmitter 135 8.1.2 Low-Power Transmitter 136 8.2 Receiver Characteristic ·…············…······· …830 137 8.2.1 High-Speed Receiver 80 138 8.2.2Low- Power receiver.................….….82 139 8.3 Line contention detection 140 8.4 Input Characteristics 84 41 9 High-Speed Data-Clock Timing 142 9.1 High-Speed Clock Timing 86 143 9.2 Forward High-Speed Data Transmission Timing 87 144 9.2.1 Data-Clock Timing Specifications 145 9.3 Reverse High-Speed Data Transmission Timing 89 146 10 Regulatory Requirements 91 147 Annex A Logical PHY-Protocol Inter face Description(informative) 92 148 A 1 Signal Description 149 A 2 High-Speed Transmit from the Master Side 150 A3 High-Speed receive at the slave Side l00 151 A 4 High-Speed Transmit from the Slave side 152 A.5 High-Speed Receive at the Master Side IOI Copyright C 2007-2009 MIPl Alliance, Inc. All rights reserved MIPI Alliance Member Confidential Version1.00.0014-May-2009 MIPI Alliance Specification for D-PHY 153 A6 Low-Power Data Transmission 102 154 A7 Low-Power Data Reception .103 155 A 8 Turn-around 156 Annex B Interconnect Design Guidelines (informative) 105 157 B. 1 Practical distances 105 158 B 2 RF Frequency Bands: Interference .105 B3 Transmission Line design 160 B4 Reference Layer .106 161 B 5 Printed-Circuit board 106 162 B6 Flex-foils 106 163 B 7 Series resistance 106 164 B 8 Connectors 106 165 Annex C 8b9b Line Coding for D-PHY(normative) 107 166 C 1 Line Coding Features... ············· 108 167 C.1.1 Enabled Features for the Protocol 108 l68 C 1. 2 Enabled Features for the Phy 108 169 C2 Coding scheme 170 C 2.1 8b9b Coding Properties.... .108 171 C 2.2 Data Codes: Basic Code Set ……….109 C.2.3 Comma Codes: Unique Exception Codes 110 173 C 2.4 Control Codes: Regular Exception Codes …10 174 C.2.5 Complete Coding Scheme……… 175 C 3 Operation with the D-PhY …111 17 yload: Data and Control 177 C.3.2 Details for Hs transmission……… 112 178 C.3.3 Details for LP Transmission l12 179 C 4 Error Signal 180 C5 Extended Ppl Copyright C 2007-2009 MIPl Alliance, Inc. All rights reserved MIPI Alliance Member Confidential Ⅴ ersion1.00.0014-May-2009 MIPI Alliance Specification for D-PHY l81 C.6 Complete Code Set.….… .l15 182 Copyright C 2007-2009 MIPl Alliance, Inc. All rights reserved MIPI Alliance Member Confidential v111 Version1.00.0014-May-2009 MIPI Alliance Specification for D-PHY l83 Figures 184 Figure 1 Universal Lane Module functions 21 185 Figure2 Two Data Lane PHY Configuration.………… 23 186 Figure 3 Option Selection Flow Graph 4 187 Figure 4 Universal Lane Module Architecture 25 188 Figure 5 Lane Symbol Macros and Symbols Legend 189 Figure 6 All Possible Data Lane Types and a basic Unidirectional Clock lane 190 Figure 7 Unidirectional Single Data Lane Configuration 30 191 Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT ∴.30 192 Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT.........31 193 Figure 10 Bidirectional Single Data Lane Configuration 31 194 Figure 1l Bi-directional Multiple Data Lane Configuration...... 32 195 Figure 12 Mixed Type multiple data Lane Configuration 32 196 Figure 13 Line level 34 197 Figure 14 High-Speed Data Transmission in Bursts 36 198 Figure 15 TX and rX State Machines for High-Speed Data Transmission 37 Figure16 Turnaround Procedure.…… 39 200 Figure 17 Turnaround State Machine 40 201 Figure 18 Trigger-Reset Command in Escape Mode 202 Figure 19 Two Data Byte Low-Power Data Transmission Example 203 Figure 20 Escape Mode State Machine 204 Figure2 I Switching the Clock Lane between Clock Transmission and low- Power mode………….47 205 Figure 22 High-Speed Clock Transmission State Machine 49 206 Figure 23 Clock Lane Ultra-Low Power State State Machine ········+·+···+·4··· 207 Figure 24 Data Lane Module State Diagram 57 208 Figure 25 Clock Lane Module state diagram 58 209 Figure 26 Point-to-point Interconnect Copyright C 2007-2009 MIPl Alliance, Inc. All rights reserved MIPI Alliance Member Confidential

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jasonzhao365 很好用的资源
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