EE141
4
VLSI Test Principles and Architectures
Test Generation
4
D Algorithm
D Algorithm
Can handle arbitrary combinational
circuits, with internal fanout structures
Main idea: always maintain a non-empty
D-frontier and try to propagate at least a
fault effect to a primary output
Initially, all circuit nodes are X, except
for the fault cite, where a fault effect (D
or D-bar) is placed.
