EE141
5
VLSI Test Principles and Architectures
Logic BIST
5
Test / Scan System
Test / Scan System
New fault tested during 1 clock vector with a complete
scan chain shift
Significantly more time required per test than test / clock
Advantage: Judicious combination of scan chains and
MISR reduces MISR bit width
Disadvantage: Much longer test pattern set length,
causes fault simulation problems
Input patterns – time shifted & repeated
Become correlated – reduces fault detection
effectiveness
Use XOR network to phase shift & decorrelate
